著者

Mitsuo Saito Takeshi Aikawa Tsukasa Matoba Mitsuyoshi Okamura Kenji Minagawa Tadatoshi Ishii

雑誌

Journal of Information Processing (ISSN:18826652)

巻号頁・発行日

vol.13, no.2, pp.144-149, 1990-08-25

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The CPU of the AI processor (AIP) called IP704 was developed for Prolog and Lisp based on RISC architecture with hardware supports. It has been proved that IP704 architecture is effective for both AI languages and general-purpose languages. An AI processor chip (IP 1704) is being developed as a direct successor of the IP704. The architecture has been modified and refined to fit onto a single chip and to improve the execution speed. Features newly developed for the IP1704 include Overlapping of the decode and register-read stages using a combination of the hardware decoder and micro-programs and a delayed cache hit check with delayed writing. Is shown that a RISC-based processor with suitable hardware support is applicable to VLSI and also gives high performance AI languages.