著者

Yuya Kono Hideyuki Kawabata Tetsuo Hironaka

出版者

Information Processing Society of Japan

雑誌

Journal of Information Processing (ISSN:18826652)

巻号頁・発行日

vol.27, pp.87-94, 2019 (Released:2019-01-15)

参考文献数

12

---

The type class mechanism, which introduces ad-hoc polymorphism into programming languages, is commonly used to realize overloading. However, this forces programmers to write many type annotations in their programs to resolve ambiguous types. Haskell's type defaulting rules reduce requirements for annotation. Furthermore, the widely used Glasgow Haskell Compiler (GHC) has an ExtendedDefaultRules (EDR) extension that facilitates interactive sessions so that the programmer avoids problems that frequently occur when using values like [] and Nothing. However, the GHC EDR extension sometimes replaces type variables with inappropriate types, so that, for example, the term show.read that is determined to have type String -> String under the GHC EDR extension does not exhibit any meaningful behavior because the function read in the term is considered to have type String -> (). We present a flexible way of resolving ambiguous types that alleviates this problem. Our proposed method does not depend on default types defined elsewhere but rather assigns a type to a type variable only when the candidate is unique. It works with any type and type class constraints. The type to be assigned is determined by scanning a list of existing type class instances that meet the type class constraints. This decision is lightweight as it is based on operations over sets without using algorithms that require backtracking. Our method is preferable to using the GHC EDR extension since it avoids the use of unnatural type variable assignments. In this paper, we describe the details of our method. We also discuss our prototype implementation that is based on the GHC plugins, and the feasibility of modifying GHC to incorporate our method.

著者

Tomoya Michinaka Hideyuki Kawabata Tetsuo Hironaka

出版者

Information Processing Society of Japan

雑誌

Journal of Information Processing (ISSN:18826652)

巻号頁・発行日

vol.29, pp.676-684, 2021 (Released:2021-10-15)

参考文献数

15

---

The GNU MPFR library for arbitrary-precision floating-point arithmetic is widely used, and its Foreign Function Interface bindings to various languages have been developed. For the Rust programming language, existing bindings to the MPFR library include gmp-mpfr-sys (a low-level binding) and Rug (a binding that utilizes gmp-mpfr-sys to provide a more user-friendly interface). However, neither has sufficient descriptiveness and performance as bindings for general users of Rust, which is a programming language featuring high memory safety and high speed. We have developed a Rust binding, Rumpfr, to the MPFR library, that offers an easy way to write programs that perform high-speed multiple-precision floating-point computation. Rumpfr provides an interface that follows that of the MPFR library but hides the complexity of managing the mantissa area of floating-point numbers from the user. Rumpfr uses Rust's variable-length arrays to allocate mantissa areas, making it easy to handle without compromising Rust's high memory safety. In this paper, we describe the design and implementation of Rumpfr and present the results of numerical experiments demonstrating that Rumpfr can be used to write programs with low overhead.

著者

Masatoshi NAKAMURA Masato INAGI Kazuya TANIGAWA Tetsuo HIRONAKA Masayuki SATO Takashi ISHIGURO

出版者

一般社団法人 電子情報通信学会

雑誌

IEICE Transactions on Information and Systems (ISSN:09168532)

巻号頁・発行日

vol.E95.D, no.2, pp.324-334, 2012-02-01 (Released:2012-02-01)

参考文献数

15

---

In this paper, we propose a placement and routing method for a new memory-based programmable logic device (MPLD) and confirm its capability by placing and routing benchmark circuits. An MPLD consists of multiple-output look-up tables (MLUTs) that can be used as logic and/or routing elements, whereas field programmable gate arrays (FPGAs) consist of LUTs (logic elements) and switch blocks (routing elements). MPLDs contain logic circuits more efficiently than FPGAs because of their flexibility and area efficiency. However, directly applying the existing placement and routing algorithms of FPGAs to MPLDs overcrowds the placed logic cells and causes a shortage of routing domains between logic cells. Our simulated annealing-based method considers the detailed wire congestion and nearness between logic cells based on the cost function and reserves the area for routing. In the experiments, our method reduced wire congestion and successfully placed and routed 27 out of 31 circuits, 13 of which could not be placed or routed using the versatile place and route tool (VPR), a well-known method for FPGAs.