著者

Ikeda H. Sano N.

出版者

IEEE

雑誌

IEEE transactions on electron devices (ISSN:00189383)

巻号頁・発行日

vol.60, no.10, pp.3417-3423, 2013-10

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We propose a surface potential-based polycrystalline silicon thin-film transistors (poly-Si TFTs) compact model considering a nonequilibrium state. A drain current model considers grain boundary (GB) trap-related physical phenomena: composite mobility of GB and intragrain, GB bias-induced mobility modulation, transient behavior because of carrier capture and emission at GBs, pinch off voltage lowering, and GB trap-assisted leakage current. Besides, photoinduced current behavior is also considered by introducing quasi-Fermi potential. A capacitance model is derived from physically partitioned terminal charges and coupled to the drain current. This compact model allows us to accurately simulate static characteristics of various types of poly-Si TFTs, including temperature and luminance dependence. Furthermore, it succeeded to simulate frequency dependence of circuit performance derived from the trap-related transient behavior, which was verified by evaluating delay time in a 21-stage inverter chain.