- 著者
-
Takuya KOMAWAKI
Michitarou YABUUCHI
Ryo KISHIDA
Jun FURUTA
Takashi MATSUMOTO
Kazutoshi KOBAYASHI
- 出版者
- The Institute of Electronics, Information and Communication Engineers
- 雑誌
- IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences (ISSN:09168508)
- 巻号頁・発行日
- vol.E100-A, no.12, pp.2758-2763, 2017-12-01
As device sizes are downscaled to nanometer, Random Telegraph Noise (RTN) becomes dominant. It is indispensable to accurately estimate the effect of RTN. We propose an RTN simulation method for analog circuits. It is based on the charge trapping model. The RTN-induced threshold voltage fluctuation are replicated to attach a variable DC voltage source to the gate of a MOSFET by using Verilog-AMS. In recent deca-nanometer processes, high-k (HK) materials are used in gate dielectrics to decrease the leakage current. We must consider the defect distribution characteristics both in HK and interface layer (IL). This RTN model can be applied to the bimodal model which includes characteristics of the HK and IL dielectrics. We confirm that the drain current of MOSFETs temporally fluctuates in circuit-level simulations. The fluctuations of RTN are different in MOSFETs. RTN affects the frequency characteristics of ring oscillators (ROs). The distribution of RTN-induced frequency fluctuations has a long-tail in a HK process. The RTN model applied to the bimodal can replicate a long-tail distribution. Our proposed method can estimate the temporal impact of RTN including multiple transistors.