著者

井上 学 小林 史典 渡邊 実

出版者

The Society of Instrument and Control Engineers

雑誌

計測自動制御学会論文集 (ISSN:04534654)

巻号頁・発行日

vol.43, no.2, pp.145-152, 2007-02-28 (Released:2013-02-25)

参考文献数

7

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A time-domain SRC, sampling rate converter, using Fourier interpolation to achieve less gate count than in frequency domain is proposed. The new SRC is implemented in 1/150 of the circuit size of conventional SRC with moderate performance using filters. It can also be used as back-end for filter-type SRC to achieve high performance efficiently.