著者

野沢 善幸

出版者

一般社団法人 日本真空学会

雑誌

Journal of the Vacuum Society of Japan (ISSN:18822398)

巻号頁・発行日

vol.53, no.7, pp.446-453, 2010 (Released:2010-08-19)

参考文献数

11

被引用文献数

1 5

---

Deep Reactive Ion Etching1-3) is well established as a commercial technique for forming Micro-Electro-Mechanical Systems (MEMS) devices. Over the last decade, development work has led to increases in silicon etch rate of an order of magnitude while requirements for etch depth uniformity and profile control have become more stringent as the wafer size has increased from 3 inch up to 200 mm.   Many MEMS devices are still etched on 150 mm wafers, while most IC devices requiring Chip Scale Package (CSP) or other processing relating to Advanced Packaging will be manufactured on 200 mm wafers with planned moves to 300 mm wafers in progress or imminent.   This paper describes the leading edge technology of Deep Si RIE including high rate etching and Through Silicon Vias (TSVs) hole formation on wafers up to 300 mm in diameter.