著者

Daniel Sangorrín Shinya Honda Hiroaki Takada

出版者

Information and Media Technologies Editorial Board

雑誌

Information and Media Technologies (ISSN:18810896)

巻号頁・発行日

vol.8, no.1, pp.1-17, 2013 (Released:2013-03-15)

参考文献数

32

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Dual-OS communications allow a real-time operating system (RTOS) and a general-purpose operating system (GPOS)—sharing the same processor through virtualization—to collaborate in complex distributed applications. However, they also introduce new threats to the reliability (e.g., memory and time isolation) of the RTOS that need to be considered. Traditional dual-OS communication architectures follow essentially the same conservative approach which consists of extending the virtualization layer with new communication primitives. Although this approach may be able to address the aforementioned reliability threats, it imposes a rather big overhead on communications due to unnecessary data copies and context switches.In this paper, we propose a new dual-OS communications approach able to accomplish efficient communications without compromising the reliability of the RTOS. We implemented our architecture on a physical platform using a highly reliable dual-OS system (SafeG) which leverages ARM TrustZone hardware to guarantee the reliability of the RTOS. We observed from the evaluation results that our approach is effective at minimizing communication overhead while satisfying the strict reliability requirements of the RTOS.

著者

Yong Xie Gang Zeng Yang Chen Ryo Kurachi Hiroaki Takada Renfa Li

雑誌

研究報告組込みシステム(EMB)

巻号頁・発行日

vol.2012-EMB-26, no.3, pp.1-8, 2012-09-03

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Controller Area Network (CAN) is widely used inside the automobiles. To decrease design complexity and cost, gateway is employed to realize the communication between different CAN buses. But its employment brings great challenges for worst-case response time (WCRT) analysis of CAN messages. We first analyzed the key challenges for WCRT analysis of messages. And then, based on existing method proposed for one single CAN, a new WCRT analysis method that considers the timing distance relations among messages is proposed for non-gateway messages. Furthermore, a division-based method that transforms the end to end WCRT analysis of gateway messages into the similar case with WCRT analysis of non-gateway messages is proposed for gateway messages. The correctness of the proposed method is proved and its usability is verified by comparing it with a full space searching based simulator as well.

著者

Yuki ANDO Seiya SHIBATA Shinya HONDA Hiroyuki TOMIYAMA Hiroaki TAKADA

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences (ISSN:09168508)

巻号頁・発行日

vol.E93-A, no.12, pp.2509-2516, 2010-12-01

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We present a hardware sharing method for design space exploration of multi-processor embedded systems. In our prior work, we had developed a system-level design tool named SystemBuilder which automatically synthesizes target implementation of a system from a functional description. In this work, we have extended SystemBuilder so that it can automatically synthesize an area-efficient implementation which shares a hardware module among different applications. With SystemBuilder, designers only need to enable an option in order to share a hardware module. The designers, therefore, can easily explore a design space including hardware sharing in short time. A case study shows the effectiveness of the hardware sharing on design space exploration.