- 著者
- Sang Muk Lee Ji Hoon Jang Jung Hwan Oh Ji Kwang Kim Seung Eun Lee
- 出版者
- 一般社団法人 電子情報通信学会
- 雑誌
- IEICE Electronics Express (ISSN:13492543)
- 巻号頁・発行日
- pp.14.20170399, (Released:2017-05-15)
- 参考文献数
- 12
- 被引用文献数
- 12
Hardware accelerators are being considered as important architectural components in the context of datacenter customization to achieve high performance and low power. Compression has played an important role in computer systems by enhancing storage and communication efficiency in the charge of extra computational cost. In this letter, we present a fully pipelined compression accelerator for the Lempel-Ziv (LZ) compression algorithm. The compression accelerator is verified by using FPGA and fabricated using 65nm CMOS technology.