- 著者
-
TAN Boon-Keat
YOSHIMURA Ryuji
MATSUOKA Toshimasa
TANIGUCHI Kenji
- 出版者
- 一般社団法人電子情報通信学会
- 雑誌
- IEICE transactions on information and systems (ISSN:09168532)
- 巻号頁・発行日
- vol.84, no.11, pp.1521-1527, 2001-11-01
- 被引用文献数
-
4
This paper describes a new architecture-based microprocessor, a dynamically programmable parallel processor (DPPP), that consists of large numbers of simplified ALUs (sALU) as processing blocks. All sALUs are interconnected via a code division multiple-access bus interface that provides complete routing flexibility by establishing connections virtually through code-matching instead of physical wires. This feature is utilized further to achieve high parallelism and fault tolerance. High fault tolerance is realized without the limitations of conventional fabrication-based techniques nor providing spare elements. Another feature of the DPPP is its simple programmability, as it can be configured by compiling numerical formula input using the provided user auto-program interface. A prototype chip based on the proposed architecture has been implemented on a 4.5 mm × 4.5 mm chip using 0.6 µm CMOS process.