著者

Jung-Dong Park

出版者

一般社団法人 電子情報通信学会

雑誌

IEICE Electronics Express (ISSN:13492543)

巻号頁・発行日

vol.11, no.18, pp.20140806-20140806, 2014 (Released:2014-09-25)

参考文献数

6

被引用文献数

1

---

Switching mode CMOS frequency multipliers are studied in sub-Terahertz regime. Analysis on the multiplier architectures and optimal gate bias at CMOS switch are investigated to maximize output power at designated harmonics. Utilizing a differential pair, a 195 GHz tripler having a hair-pin filter is designed to maximize 3rd harmonics with −14.8 dB of conversion gain (CG) from Pin = +13 dBm of the balanced input, while the 260 GHz quadrupler utilizes quadruple-push pairs which achieves CG = −16 dB from two +13 dBm of the balanced I/Q driving signals in a 65 nm digital CMOS process.