著者
Daisuke Oguchi Satoshi Moriya Hideaki Yamamoto Shigeo Sato
出版者
The Institute of Electronics, Information and Communication Engineers
雑誌
Nonlinear Theory and Its Applications, IEICE (ISSN:21854106)
巻号頁・発行日
vol.13, no.2, pp.427-433, 2022 (Released:2022-04-01)
参考文献数
10
被引用文献数
1

Reinforcement learning is promising as a machine learning paradigm in edge computing. However, its high computational cost poses a challenge when implementing in devices with limited circuit resources and power consumption. In this study, we investigated the relationship between the bit-length of floating-point operations and the learning performance of the reinforcement learning algorithm. In the case of the FrozenLake maze problem, we found that the learning performance of 8-bit floating-point arithmetic decreased, while that of 16-bit floating-point arithmetic was comparable to that of 64-bit CPU arithmetic. Our results provide a practical guideline for designing a dedicated reinforcement learning hardware with minimum circuit resources and power consumption.

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J-STAGE Articles - An investigation of the relationship between numerical precision and performance of Q-learning for hardware implementation https://t.co/HLHrb95KKw

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