著者

Abe Shin-ya Shi Youhua Yanagisawa Masao Togawa Nozomu

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE Electronics Express (ISSN:13492543)

巻号頁・発行日

vol.9, no.17, pp.1414-1422, 2012

被引用文献数

14

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In this paper, we propose multiple-supply-voltages aware high-level synthesis algorithm for <i>HDR architectures</i> which realizes high-speed and high-efficient circuits. We propose three new techniques: <i>virtual area estimation</i>, <i>virtual area adaptation</i>, and <i>floor-planning-directed huddling</i>, and integrate them into our HDR architecture synthesis algorithm. Virtual area estimation/adaptation effectively estimates a huddle area by gradually reducing it during iterations, which improves the convergence of our algorithm. Floorplanning-directed huddling determines huddle composition very effectively by performing floorplanning and functional unit assignment inside huddles simultaneously. Experimental results show that our algorithm achieves about 29% run-time-saving compared with the conventional algorithms, and obtains a solution which cannot be obtained by our original algorithm even if a very tight clock constraint is given.