著者

Lee Hu-ung Lee Seongjing Kim Jae-woon Won Youjip

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE Electronics Express (ISSN:13492543)

巻号頁・発行日

vol.12, no.12, pp.20150371-20150371, 2015

被引用文献数

3

---

In this paper, we propose the parallel architecture for high speed calculations of SHA-1, a widely used cryptographic hash function. Parallel SHA-1 consists of a number of base modules which process the message digest in parallel manner. The base module uses state of art SHA-1 acceleration techniques: loop unfolding, pre-processing, and pipelining. We achieved the performance improvement of 5.8% over the pipeline architecture that is known to have nearly achieved the theoretical performance limit. We implemented our system on the Xilinx Virtex-6 FPGA and verified the operations by interfacing it with MicroBlaze soft processor core.