著者

Kasahara S. Watashige T. Hanaguri T. Kohsaka Y. Yamashita T. Shimoyama Y. Mizukami Y. Endo R. Ikeda H. Aoyama K. Terashima T. Uji S. Wolf T. von Lohneysen H. Shibauchi T. Matsuda Y.

出版者

National Academy of Sciences

雑誌

Proceedings of the National Academy of Sciences (ISSN:00278424)

巻号頁・発行日

vol.111, no.46, pp.16309-16313, 2014-11

被引用文献数

315

---

「ボース・アインシュタイン凝縮に最も近い超伝導状態」を発見. 京都大学プレスリリース. 2014-11-05.

著者

Tonegawa S Kasahara S Fukuda T Sugimoto K Yasuda N Tsuruhara Y Watanabe D Mizukami Y Haga Y Matsuda T D Yamamoto E Onuki Y Ikeda H Matsuda Y Shibauchi T

出版者

Nature Publishing Group

雑誌

Nature communications (ISSN:20411723)

巻号頁・発行日

vol.5, 2014-06-19

被引用文献数

57

---

直接観測された物質物理学の謎「隠れた秩序」. 京都大学プレスリリース. 2014-06-19.

著者

Ikeda H. Sano N.

出版者

IEEE

雑誌

IEEE transactions on electron devices (ISSN:00189383)

巻号頁・発行日

vol.60, no.10, pp.3417-3423, 2013-10

---

We propose a surface potential-based polycrystalline silicon thin-film transistors (poly-Si TFTs) compact model considering a nonequilibrium state. A drain current model considers grain boundary (GB) trap-related physical phenomena: composite mobility of GB and intragrain, GB bias-induced mobility modulation, transient behavior because of carrier capture and emission at GBs, pinch off voltage lowering, and GB trap-assisted leakage current. Besides, photoinduced current behavior is also considered by introducing quasi-Fermi potential. A capacitance model is derived from physically partitioned terminal charges and coupled to the drain current. This compact model allows us to accurately simulate static characteristics of various types of poly-Si TFTs, including temperature and luminance dependence. Furthermore, it succeeded to simulate frequency dependence of circuit performance derived from the trap-related transient behavior, which was verified by evaluating delay time in a 21-stage inverter chain.