- 著者
- Dashan Shi Jia Yuan Jialu Yin Yulian Wang Shushan Qiao
- 出版者
- The Institute of Electronics, Information and Communication Engineers
- 雑誌
- IEICE Electronics Express (ISSN:13492543)
- 巻号頁・発行日
- vol.19, no.10, pp.20220089, 2022-05-25 (Released:2022-05-25)
- 参考文献数
- 37
- 被引用文献数
- 2
This paper presents a half-selected robust 12T bitcell with built-in write-assist for sub-threshold SRAM. The proposed 12T bitcell is robust enough in bit-interleaving architecture to enhance soft-error immunity combined with error correction code. The read stability of the proposed bitcell is improved by read decoupled. The writability is improved by data-dependent supply-cutoff write-assist. Both row and column f-selected bitcells can hold data stably during write operations. Simulation results based on a standard 55nm CMOS technology show that the read static noise margin of the proposed bitcell is 16.13x as that of the conventional 6T bitcell. Moreover, the write failure in the sub-threshold region is eliminated. In addition, the leakage consumption is improved by 15.7% compared with 6T bitcell.
- 著者
- Zhi Li Huidong Zhao Jialu Yin Shushan Qiao Yumei Zhou
- 出版者
- The Institute of Electronics, Information and Communication Engineers
- 雑誌
- IEICE Electronics Express (ISSN:13492543)
- 巻号頁・発行日
- vol.19, no.11, pp.20220102, 2022-06-10 (Released:2022-06-10)
- 参考文献数
- 30
- 被引用文献数
- 2
A fully integrated CMOS RC oscillator is presented. The oscillator is inverter-based. An adaptive body biasing (ABB) scheme is proposed to regulate the trip point of the decision inverter adaptively, thus alleviating the frequency variation over PVT. To achieve low power consumption all components are in the sub-threshold region. The circuit is designed in a 55-nm CMOS process with an area of 0.052mm2. The simulation result shows a temperature sensitivity of 59ppm/°C from -40∼125°C which achieves a 72ppm/°C reduction as compared to an oscillator without ABB. the oscillator operates at 33kHz and consumes 183nW from a 0.6V supply.