著者

Lingyan Fan Jianjun Luo Hailuan Liu Xuan Geng

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE Electronics Express (ISSN:13492543)

巻号頁・発行日

vol.11, no.13, pp.20140535-20140535, 2014 (Released:2014-07-10)

参考文献数

6

被引用文献数

3

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AES has been one of the most popular encryption and decryption algorithms for data security applications. At the same time, data randomization (or “homogeneous”) technology was applied to reduce the bit error rate (BER) of MLC and TLC flash memory. Here, AES algorithm was found efficient to replace the orthogonal polynomials which normally carry out homogeneous function by scrambling data. This paper put forward a novel hardware architecture providing both homogeneous and data encryption/decryption functions concurrently by an embedded AES hardware engine while getting rid of randomization engine with Linear Feedback Shift Register (LFSR). It made a flash controller simple and reduced the die size because the independent homogeneous hard engine is no longer necessary for a flash memory system, in which AES security algorithm embedded. Finally a SSD controller designed in this architecture was silicon proven.