著者

Ishibashi Koichiro Komiyaji Kunihiro Morita Sadayuki Aoto Toshiro Ikeda Shuji Asayama Kyoichiro Koike Atsuyosi Yamanaka Toshiaki Hashimoto Naotaka Iida Haruhito Kojima Fumio Motohashi Koichi Sasaki Katsuro

出版者

一般社団法人電子情報通信学会

雑誌

IEICE transactions on electronics (ISSN:09168524)

巻号頁・発行日

vol.77, no.5, pp.741-748, 1994-05-25

被引用文献数

26

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A 16-Mb CMOS SRAM using 0.4-μm CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm^2 is fabricated and an address access time of 12.5 ns has been achieved.