著者

Kentaro YOSHIOKA

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE Transactions on Electronics (ISSN:09168524)

巻号頁・発行日

pp.2021CTI0002, (Released:2022-04-11)

被引用文献数

4

---

LiDAR is a distance sensor that plays a key role in the realization of advanced driver assistance systems (ADAS). In this paper, we present a tutorial and review of automotive direct time of flight (dToF) LiDAR from the aspect of circuit systems. We discuss the breakthrough in ADAS LiDARs through comparison with the first-generation LiDAR systems, which were conventionally high-cost and had an immature performance. We define current high-performance and low-cost LiDARs as next-generation LiDAR systems, which have significantly improved the cost and performance by integrating the photodetector, the readout circuit, and the signal processing unit into a single SoC.This paper targets reader who is new to ADAS LiDARs and will cover the basic principles of LiDAR, also comparing with range methods other than dToF. In addition, we discuss the development of this area through the latest research examples such as the 2-chip approach, 2D SPAD array, and 3D integrated LiDARs.

著者

Takashi SHIBATA Kazunori SATO Ryohei IKEJIRI

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE Transactions on Electronics (ISSN:09168524)

巻号頁・発行日

vol.E100.C, no.11, pp.1012-1020, 2017-11-01 (Released:2017-11-01)

参考文献数

20

被引用文献数

2

---

We conducted experimental classes in an elementary school to examine how the advantages of using stereoscopic 3D images could be applied in education. More specifically, we selected a unit of the Tumulus period in Japan for sixth-graders as the source of our 3D educational materials. This unit represents part of the coursework for the topic of Japanese history. The educational materials used in our study included stereoscopic 3D images for examining the stone chambers and Haniwa (i.e., terracotta clay figures) of the Tumulus period. The results of our experimental class showed that 3D educational materials helped students focus on specific parts in images such as attached objects of the Haniwa and also understand 3D spaces and concavo-convex shapes. The experimental class revealed that 3D educational materials also helped students come up with novel questions regarding attached objects of the Haniwa, and Haniwa's spatial balance and spatial alignment. The results suggest that the educational use of stereoscopic 3D images is worthwhile in that they lead to question and hypothesis generation and an inquiry-based learning approach to history.

著者

Ryo KITAMURA Koichiro TANAKA Tadashi MORITA Takayuki TSUKIZAWA Koji TAKINAMI Noriaki SAITO

出版者

一般社団法人 電子情報通信学会

雑誌

IEICE Transactions on Electronics (ISSN:09168524)

巻号頁・発行日

vol.E96.C, no.10, pp.1301-1310, 2013-10-01 (Released:2013-10-01)

参考文献数

14

被引用文献数

3 4 1

---

This paper presents an automatic gain control (AGC) system suitable for 60GHz direct conversion receivers. By using a two step gain control algorithm with high-pass filter cutoff frequency switching, the proposed AGC system realizes fast settling time and wide dynamic range simultaneously. The paper also discusses wide-bandwidth variable gain amplifier (VGA) design. By introducing digitally-controlled resistors and gain flattening capacitors, the proposed VGA realizes wide gain range while compensating gain variations due to parasitic capacitance of MOS switches. The AGC system is implemented in a transceiver chipset where RFIC and BBIC are fabricated in 90nm CMOS and 40nm CMOS respectively. The measurement shows excellent dynamic range of 47dB with +/-1dB gain accuracy within 1µs settling time, which satisfies the stringent requirements of the IEEE802.11ad standard.

著者

TIEN DAT Pham KANNO Atsushi KAWANISHI Tetsuya

出版者

一般社団法人 電子情報通信学会

雑誌

IEICE Transactions on Electronics (ISSN:09168524)

巻号頁・発行日

vol.99, no.2, pp.331_e1-331_e1, 2016

著者

FIORI Franco CROVETTI Paolo S.

出版者

一般社団法人電子情報通信学会

雑誌

IEICE transactions on electronics (ISSN:09168524)

巻号頁・発行日

vol.86, no.11, pp.2309-2319, 2003-11-01

被引用文献数

1

---

In this paper a second order Volterra series model of an operational amplifier (opamp) circuit is presented. Such a model is suitable to the investigation of the rectification and demodulation effects of radio frequency (RF) interference superimposed on the nominal input signals and on the power supply voltage of an opamp. On the basis of the new model, some design criteria to improve the immunity of opamps to RF interference are proposed. Model predictions are verified by comparison with experimental test results.

著者

Peijian Zhang Kunfeng Zhu Wensuo Chen

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE Transactions on Electronics (ISSN:09168524)

巻号頁・発行日

pp.2022ECP5059, (Released:2023-07-04)

---

In this paper, a novel trench MOS barrier Schottky contact super barrier rectifier (TMB-SSBR) is proposed by combining the advantages of vertical SSBR and conventional TMBS. The operation mechanism and simulation verification are presented. TMB-SSBR consists of MOS trenches with a vertical SSBR grid which replaces the Schottky diode in the mesa of a TMBS. Due to the presence of top p-n junction in the proposed TMB-SSBR, the image force barrier lowering effect is eliminated, the pinching off electric field effect by MOS trenches is weakened, so that the mesa surface electric field is much larger than that in conventional TMBS. Therefore, the mesa width is enlarged and the n-drift concentration is slightly increased, which results in a low specific on-resistance and a good tradeoff between reverse leakage currents and forward voltages. Compared to a conventional TMBS, simulation results show that, with the same breakdown voltage of 124 V and the same reverse leakage current at room temperature, TMB-SSBR increases the figure of merit (FOM, equates to VB2/Ron,sp) by 25.5%, and decreases the reverse leakage by 33.3% at the temperature of 423 K. Just like the development from SBD to TMBS, from TMBS to TMB-SSBR also brings obvious improvement of performance.

著者

Kota SHIBA Atsutake KOSUGE Mototsugu HAMADA Tadahiro KURODA

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE Transactions on Electronics (ISSN:09168524)

巻号頁・発行日

pp.2022CDS0001, (Released:2022-09-30)

---

This paper describes an in-depth analysis of crosstalk in a high-bandwidth 3D-stacked memory using a multi-hop inductive coupling interface and proposes two countermeasures. This work analyzes the crosstalk among seven stacked chips using a 3D electromagnetic (EM) simulator. The detailed analysis reveals two main crosstalk sources: concentric coils and adjacent coils. To suppress these crosstalks, this paper proposes two corresponding countermeasures: shorted coils and 8-shaped coils. The combination of these coils improves area efficiency by a factor of 4 in simulation. The proposed methods enable an area-efficient inductive coupling interface for high-bandwidth stacked memory.

著者

Shuhei AMAKAWA

出版者

一般社団法人 電子情報通信学会

雑誌

IEICE Transactions on Electronics (ISSN:09168524)

巻号頁・発行日

vol.E99.C, no.10, pp.1100-1112, 2016-10-01 (Released:2016-10-01)

参考文献数

79

被引用文献数

7

---

The most commonly used scattering parameters (S parameters) are normalized to a real reference resistance, typically 50Ω. In some cases, the use of S parameters normalized to some complex reference impedance is essential or convenient. But there are different definitions of complex-referenced S parameters that are incompatible with each other and serve different purposes. To make matters worse, different simulators implement different ones and which ones are implemented is rarely properly documented. What are possible scenarios in which using the right one matters? This tutorial-style paper is meant as an informal and not overly technical exposition of some such confusing aspects of S parameters, for those who have a basic familiarity with the ordinary, real-referenced S parameters.

著者

Kouji Shibata

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE Transactions on Electronics (ISSN:09168524)

巻号頁・発行日

pp.2020ECP5025, (Released:2020-08-14)

被引用文献数

4

---

A method for the calibration of S11 at the front surface of a material for a coaxial-feed type cut-off circular waveguide with three reference materials inserted and no short termination condition was proposed as a preliminary step for dielectric measurement in liquids. The equations for jig calibration of S11 with these reference materials were first defined, and the electrostatic capacitance for the analytical model unique to the jig was quantified by substituting the reflection constant (calculated at frequencies of 0.50, 1.5 and 3.0 GHz using the mode-matching (MM) technique) into the equivalent circuit, assuming the sample liquid in the jig. The accuracy of S11 measured using the proposed method was then verified. S11 for the front surface of the sample material was also measured with various liquids in the jig after calibration, and the dielectric constants of the liquids were estimated as an inverse problem based on comparison of S11 calculated from an analytical model using EM analysis via the MM technique with the measured S11 values described above. The effectiveness of the proposed S11 calibration method was verified by comparison with dielectric constants estimated after S11 SOM (short, open and reference material) calibration and similar, with results showing favorable agreement with each method.

著者

SUHARA Keiichi

出版者

一般社団法人電子情報通信学会

雑誌

IEICE transactions on electronics (ISSN:09168524)

巻号頁・発行日

vol.88, no.8, pp.1603-1615, 2005-08-01

被引用文献数

8

---

Short gap arc V-I characteristics are essential to discussions on behavior of contact arc at opening and closing. From this point of view, some conventional arc V-I characteristics were reviewed and inconvenient points of them for practical use were pointed out : (1) not a few electrode-material-dependent constants needed in the equation of V-I relation, (2) difficulty in the prediction of real arc extinction phenomena. In order to overcome these inconveniences, the author measured short gap arc V-I characteristics originally, and tried to formulate them into a simple form on the assumption that the arc column V-I characteristics are little dependent on electrode materials but the unstable arc region is strongly dependent on electrode materials. Measured arc column voltage was directly proportional to the square root of gap length and inversely proportional to the cube root of arc current. Arc became unstable when arc current decreased near to the value generally known as the minimum arc current. It was not necessarily the case that the arc extinguished completely at the minimum arc current, but, depending on the circuit conditions, the arc often existed discontinuously below the so-called minimum arc current. Simple empirical V-I characteristics were proposed for practical use, together with the unstable arc region as the information for arc extinction phenomena.

著者

Shuping ZHANG Jinjia ZHOU Dajiang ZHOU Shinji KIMURA Satoshi GOTO

出版者

一般社団法人 電子情報通信学会

雑誌

IEICE Transactions on Electronics (ISSN:09168524)

巻号頁・発行日

vol.E100.C, no.3, pp.223-231, 2017-03-01 (Released:2017-03-01)

参考文献数

31

---

In this paper, a hamburger architecture with a 3D stacked reconfigurable memory is proposed for a 4K motion estimation (ME) processor. By positioning the memory dies on both the top and bottom sides of the processor die, the proposed hamburger architecture can reduce the usage of the signal through-silicon via (TSV), and balance the power delivery network and the clock tree of the entire system. It results in 1/3 reduction of the usage of signal TSVs. Moreover, a stacked reconfigurable memory architecture is proposed to reduce the fabrication complexity and further reduce the number of signal TSVs by more than 1/2. The reduction of signal TSVs in the entire design is 71.24%. Finally, we address unique issues that occur in electronic design automation (EDA) tools during 3D large-scale integration (LSI) designs. As a result, a 4K ME processor with 7-die stacking 3D system-on-chip design is implemented. The proposed design can support real time 3840 × 2160 @ 120 fps encoding at 130 MHz with less than 540 mW.

著者

Asada Kunihiro Akita Junichi

出版者

一般社団法人電子情報通信学会

雑誌

IEICE transactions on electronics (ISSN:09168524)

巻号頁・発行日

vol.78, no.4, pp.436-440, 1995-04-25

被引用文献数

7

---

Some CMOS gates are topologically asymmetric in inputs, even though they are logically symmetric. It implies a possibility to reduce power consumption by optimizing signal assignment to the inputs. In this study we theoretically derive power consumption of 2-input NAND gate based on transition probability of input signals, with taking into account charging current due to an internal node. We also propose a signal assignment method to input terminals for reducing power consumption reduction by extending our method for large circuits, and demonstrate the effect of power consumption reduction by the present method.

著者

Ishibashi Koichiro Komiyaji Kunihiro Morita Sadayuki Aoto Toshiro Ikeda Shuji Asayama Kyoichiro Koike Atsuyosi Yamanaka Toshiaki Hashimoto Naotaka Iida Haruhito Kojima Fumio Motohashi Koichi Sasaki Katsuro

出版者

一般社団法人電子情報通信学会

雑誌

IEICE transactions on electronics (ISSN:09168524)

巻号頁・発行日

vol.77, no.5, pp.741-748, 1994-05-25

被引用文献数

26

---

A 16-Mb CMOS SRAM using 0.4-μm CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm^2 is fabricated and an address access time of 12.5 ns has been achieved.

著者

UCHIDA Teiji MIKAMI Osamu

出版者

一般社団法人電子情報通信学会

雑誌

IEICE transactions on electronics (ISSN:09168524)

巻号頁・発行日

vol.80, no.1, pp.81-87, 1997-01-25

参考文献数

13

被引用文献数

34

---

Optical surface mount technology (O-SMT), which was proposed to provide a possible solution to growing serious problems in manufacturing process of optoelectronic products, is introduced. After discussing the basic idea of O-SMT, experimental results are also described to show its feasibility.

著者

Md. Mottaleb HOSSAIN Md. Abdullah-AL HUMAYUN Md. Tanvir HASAN Ashraful Ghani BHUIYAN Akihiro HASHIMOTO Akio YAMAMOTO

出版者

一般社団法人 電子情報通信学会

雑誌

IEICE Transactions on Electronics (ISSN:09168524)

巻号頁・発行日

vol.E95.C, no.2, pp.255-261, 2012-02-01 (Released:2012-02-01)

参考文献数

26

被引用文献数

2 9

---

This paper reports on a theoretical study and modeling of a 1.55µm quantum dot heterostructure laser using InN as a promising candidate for the first time. Details of design and theoretical analysis of probability distribution of the optical transition energy, threshold current density, modal gain, and differential quantum efficiency are presented considering a single layer of quantum dots. Dependence of threshold current density on the RMS value of quantum dot size fluctuations and the cavity length is studied. A low threshold current density of ∼51Acm-2 is achieved at room temperature for a cavity length of 640µm. An external differential efficiency of ∼65% and a modal gain of ∼12.5cm-1 are obtained for the proposed structure. The results indicate that the InN based quantum dot laser is a promising one for the optical communication system.

著者

AKIMA Hisanao SATO Shigeo NAKAJIMA Koji

出版者

一般社団法人電子情報通信学会

雑誌

IEICE transactions on electronics (ISSN:09168524)

巻号頁・発行日

vol.87, no.5, pp.832-834, 2004-05-01

被引用文献数

1

---

A random number generator composed of single electron devices is presented. Due to stochastic behavior of electron tunneling process, single electron devices have intrinsic randomness. Using its randomness, a true random number generator can be implemented. Although fluctuation of device parameters degrades the performance of the proposed circuit, we show that the adjustment of the bias voltages can compensate the fluctuation.

著者

LI Keren

出版者

一般社団法人電子情報通信学会

雑誌

IEICE transactions on electronics (ISSN:09168524)

巻号頁・発行日

vol.81, no.12, pp.1845-1851, 1998-12-25

---

In this paper, we present an analysis of the microstrip lines whose strip conductors are of various cross-sections, such as rectangular cross-section, triangle cross-section, and half-cycle cross-section. The method employed is the boundary integral equation method (BIEM). Numerical results for these microstrip lines demonstrate various shape effects of the strip conductor on the characteristics of lines. The processing technique on the convergence of the Green's function is also described.

著者

OHTSUKI Masaaki KAWAI Masato FUKUI Masahiro

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE transactions on electronics (ISSN:09168524)

巻号頁・発行日

vol.92, no.4, pp.500-507, 2009-04-01

被引用文献数

4 5

---

Accompanying with the popularization of portable equipments, and the rapid growth of the size of the electric systems, efficient low power design methodologies have been highly required. To satisfy these requests, a high accurate and high efficient power analysis in higher abstraction level is very important. The design environment is composed by efficient algorithms of power modeling, power library building, and data extracting. Those components of the environment should be balanced for the total efficiency and accuracy. We have proposed a new efficient power modeling environment which uses a look-up table (LUT). It reduces the size of the LUT drastically, compared to conventional algorithms. It makes the power analysis and library building high efficient. The experimental results show that our approach reduces the computation time to build the library to one tenth while keeping the accuracy of the power analysis. The RMS error and the largest error has been less than 8.30%, 59.16%, respectively.

著者

HANYU Takahiro KAMEYAMA Michitaka

出版者

一般社団法人電子情報通信学会

雑誌

IEICE transactions on electronics (ISSN:09168524)

巻号頁・発行日

vol.82, no.9, pp.1662-1668, 1999-09-25

被引用文献数

12

---

A new logic-in-memory VLSI architecture based on multiple-valued floating-gate-MOS pass-transistor logic is proposed to solve the communication bottleneck between memory and logic modules. Multiple-valued stored data are represented by the threshold voltage of a floating-gate MOS transistor, so that a single floating-gate MOS transistor is effectively employed to merge multiple-valued threshold-literal and pass-switch functions. As an application, a four-valued logicin-memory VLSI for high-speed pattern recognition is also presented. The proposed VLSI detects a stored reference word with the minimum Manhattan distance between a 16-bit input word and 16-bit stored reference words. The effective chip area, the switching delay and the power dissipation of a new four-valued full adder, which is a key component of the proposed logic-in-memory VLSI, are reduced to about 33 percent, 67 percent and 24 percent, respectively, in comparison with those of the corresponding binary CMOS implementation under a 0.5-μm flash EEPROM, technology.