- 著者
- Puqing Yang Zhaofeng Zhang
- 出版者
- The Institute of Electronics, Information and Communication Engineers
- 雑誌
- IEICE Electronics Express (ISSN:13492543)
- 巻号頁・発行日
- vol.19, no.18, pp.20220337, 2022-09-25 (Released:2022-09-25)
- 参考文献数
- 31
- 被引用文献数
- 2
This paper presents a novel first-order noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC) for passive wireless sensor node application. To decrease dynamic power consumption, one-side switching instead (OSSI) method and higher-bit switching instead (HBSI) method are adopted in our proposed noise-shaping architecture. Dynamic SAR logic and dynamic comparator are used to further reduce power consumption. In addition, a low supply voltage is applied to this ADC, which can decrease static current leakage. The proposed noise-shaping SAR ADC was fabricated in 0.18um 1P4M CMOS technology, which occupies an active area of 0.185mm2. The prototype chip consumes 89nW at 25kHz sampling rate. The measurement shows 58.2dB signal to noise and distortion ratio (SNDR) can be achieved.