- 著者
-
Shuping ZHANG
Jinjia ZHOU
Dajiang ZHOU
Shinji KIMURA
Satoshi GOTO
- 出版者
- 一般社団法人 電子情報通信学会
- 雑誌
- IEICE Transactions on Electronics (ISSN:09168524)
- 巻号頁・発行日
- vol.E100.C, no.3, pp.223-231, 2017-03-01 (Released:2017-03-01)
- 参考文献数
- 31
In this paper, a hamburger architecture with a 3D stacked reconfigurable memory is proposed for a 4K motion estimation (ME) processor. By positioning the memory dies on both the top and bottom sides of the processor die, the proposed hamburger architecture can reduce the usage of the signal through-silicon via (TSV), and balance the power delivery network and the clock tree of the entire system. It results in 1/3 reduction of the usage of signal TSVs. Moreover, a stacked reconfigurable memory architecture is proposed to reduce the fabrication complexity and further reduce the number of signal TSVs by more than 1/2. The reduction of signal TSVs in the entire design is 71.24%. Finally, we address unique issues that occur in electronic design automation (EDA) tools during 3D large-scale integration (LSI) designs. As a result, a 4K ME processor with 7-die stacking 3D system-on-chip design is implemented. The proposed design can support real time 3840 × 2160 @ 120 fps encoding at 130 MHz with less than 540 mW.