著者

Trong-Thuc Hoang Ckristian Duran Khai-Duy Nguyen Tuan-Kiet Dang Quynh Nguyen Quang Nhu Phuc Hong Than Xuan-Tu Tran Duc-Hung Le Akira Tsukamoto Kuniyasu Suzaki Cong-Kha Pham

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE Electronics Express (ISSN:13492543)

巻号頁・発行日

pp.17.20200282, (Released:2020-10-06)

参考文献数

30

被引用文献数

7

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In this paper, a 32-bit RISC-V microcontroller in a 65-nm Silicon-On-Thin-BOX (SOTB) chip is presented. The system is developed based on the VexRiscv Central Processing Unit (CPU) with the Instruction Set Architecture (ISA) extensions of RV32IM. Besides the core processor, the System-on-Chip (SoC) contains 8KB of boot ROM, 64KB of on-chip memory, UART controller, SPI controller, timer, and GPIOs for LEDs and switches. The 8KB of boot ROM has 7KB of hard-code in combinational logics and 1KB of a stack in SRAM. The proposed SoC performs the Dhrystone and Coremark benchmarks with the results of 1.27 DMIPS/MHz and 2.4 Coremark/MHz, respectively. The layout occupies 1.32-mm2 of die area, which equivalents to 349,061 of NAND2 gate-counts. The 65-nm SOTB process is chosen not only because of its low-power feature but also because of the back-gate biasing technique that allows us to control the microcontroller to favor the low-power or the high-performance operations. The measurement results show that the highest operating frequency of 156-MHz is achieved at 1.2-V supply voltage (VDD) with +1.6-V back-gate bias voltage (VBB). The best power density of 33.4-µW/MHz is reached at 0.5-V VDD with +0.8-V VBB. The least current leakage of 3-nA is retrieved at 0.5-V VDD with -2.0-V VBB.