著者

Asada Kunihiro Akita Junichi

出版者

一般社団法人電子情報通信学会

雑誌

IEICE transactions on electronics (ISSN:09168524)

巻号頁・発行日

vol.78, no.4, pp.436-440, 1995-04-25

被引用文献数

7

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Some CMOS gates are topologically asymmetric in inputs, even though they are logically symmetric. It implies a possibility to reduce power consumption by optimizing signal assignment to the inputs. In this study we theoretically derive power consumption of 2-input NAND gate based on transition probability of input signals, with taking into account charging current due to an internal node. We also propose a signal assignment method to input terminals for reducing power consumption reduction by extending our method for large circuits, and demonstrate the effect of power consumption reduction by the present method.