著者

Zawawi Ruhaifi Abdullah Zulkifli Tun Zainal Azni

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE Electronics Express (ISSN:13492543)

巻号頁・発行日

vol.11, no.12, pp.20140383, 2014

被引用文献数

1

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A new CMOS bandgap voltage reference (BGR) is proposed and simulated using Silterra 0.13 µm CMOS technology. The proposed BGR utilizes 3 curvature-corrected current generators that compensate for the output voltage variation in an extended temperature range. The proposed circuit generates an output voltage of 1.181 V with a variation of 380 µV from −50 °C to 150 °C.

著者

Zawawi Ruhaifi Abdullah Sidek Othman Hassin Wan Mohd Hafizi Wan Zulkipli Mohamad Izat Amir Rhaffor Nuha

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE Electronics Express (ISSN:13492543)

巻号頁・発行日

vol.8, no.22, pp.1876-1881, 2011

被引用文献数

5

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In the current paper, an improvement of piecewise curvature-corrected CMOS bandgap reference (BGR) circuit is proposed. The circuit utilizes piecewise nonlinear curvature-corrected current (PNCCC) in a conventional BGR with a current control circuit, which compensates for the voltage reference at a higher temperature range. The current control circuit (CCC) is used to reduce the total current at low temperature when the PNCCC generator is inactive. The proposed circuit is realized in CMOS 0.13µm and has been verified to be able to save power consumption by 18.6% compared with a circuit without the current control circuit.

著者

Zawawi Ruhaifi Abdullah Sidek Othman

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE Electronics Express (ISSN:13492543)

巻号頁・発行日

vol.9, no.4, pp.240-244, 2012

被引用文献数

10

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The current paper presents an improved bandgap voltage reference (BGR) that utilizes curvature-corrected current generators which compensate for the voltage reference at lower and higher temperature range. The voltage reference is operated with a supply voltage of 2.5V to achieve an output reference of 1.1835V. The temperature coefficient achieved from the circuit is 1.342ppm/°C, resulting from temperature changes between -50°C to 125°C, sixfold improvement from first-order BGR. The proposed circuit is simulated using Silterra 0.13µm CMOS technology.