著者
IKUO TAKEUCHI YOSHIJI AMAGAI MASAHARU YOSHIDA KENICH YAMAZAKI
出版者
一般社団法人情報処理学会
雑誌
情報処理学会論文誌プログラミング(PRO) (ISSN:18827802)
巻号頁・発行日
vol.44, no.16, pp.41-55, 2003-12-15

In this presentation we report on the microprogramming implementation and its evaluation of a concurrent real-time garbage collector (GC)for the rea-time symbolic processing system TAO/SILENT. Our real-time GC is implemented as a set of GC processes which run concurrently with other Lisp processes. It is based upon a sort of well-known incremental update algorithm and it brings in only a little overhead to Lisp primitives. We embedded a scheduling mechanism that is speci fic to GC process scheduling since it is indispensable to devise a good cooperation scheme between the operating system kernel and concurrent GC. We also developed a good deal of tiny techniques to make the GC processes as swift as possible. As a result our concurrent GC achieves a very small response delay for external events that is when an interrupt event takes place the corresponding urgent Lisp process can wake up in less than 131 microseconds for the worst case where more than ten thousand memory-consuming Lisp processes are concurrently running and surely in less than 50 microseconds if those Lisp processes are made with real-time consciousness. These figures are more than a hundred times as good as most of those appeared in the literature. Our GC can be said "transparent"in the sense that real-time processes would not be aware of the GC whether it runs or not at least with respect to response delay.In this presentation,we report on the microprogramming implementation and its evaluation of a concurrent real-time garbage collector (GC)for the rea-time symbolic processing system TAO/SILENT. Our real-time GC is implemented as a set of GC processes which run concurrently with other Lisp processes. It is based upon a sort of well-known incremental update algorithm, and it brings in only a little overhead to Lisp primitives. We embedded a scheduling mechanism that is speci fic to GC process scheduling, since it is indispensable to devise a good cooperation scheme between the operating system kernel and concurrent GC. We also developed a good deal of tiny techniques to make the GC processes as swift as possible. As a result, our concurrent GC achieves a very small response delay for external events, that is, when an interrupt event takes place, the corresponding urgent Lisp process can wake up in less than 131 microseconds for the worst case where more than ten thousand memory-consuming Lisp processes are concurrently running, and surely in less than 50 microseconds if those Lisp processes are made with real-time consciousness. These figures are more than a hundred times as good as most of those appeared in the literature. Our GC can be said "transparent"in the sense that real-time processes would not be aware of the GC whether it runs or not, at least with respect to response delay.
著者
Yasushi Hibino Kazufumi Watanabe Ikuo Takeuchi
出版者
一般社団法人情報処理学会
雑誌
情処学論 (ISSN:18826652)
巻号頁・発行日
vol.13, no.2, pp.156-164, 1990-08-25
被引用文献数
3

This paper describes a 32-bit LISP processor chip developed for the AI workstation ELIS with the multiple programming paradigm language TAO. The objective of this microprocessor is to realize an S-expression machine that can match the speed of conventional machines for compiled code execution. Architectural features are a repetitive structure for VLSI implementation of the tagged architecture and a dedicated datapath for list manipulation. All the processor functions are realized on a single VLSI chip that uses a 2-micron CMOS process. ELIS supports not only LISP but also multiple programming paradigms. The ELIS interpreter has a higher performance than that of any other dedicated machine on the market.This paper describes a 32-bit LISP processor chip developed for the AI workstation ELIS with the multiple programming paradigm language TAO. The objective of this microprocessor is to realize an S-expression machine that can match the speed of conventional machines for compiled code execution. Architectural features are a repetitive structure for VLSI implementation of the tagged architecture and a dedicated datapath for list manipulation. All the processor functions are realized on a single VLSI chip that uses a 2-micron CMOS process. ELIS supports not only LISP but also multiple programming paradigms. The ELIS interpreter has a higher performance than that of any other dedicated machine on the market.
著者
Yasushi Hibino Kazufumi Watanabe Ikuo Takeuchi
雑誌
Journal of Information Processing (ISSN:18826652)
巻号頁・発行日
vol.13, no.2, pp.156-164, 1990-08-25

This paper describes a 32-bit LISP processor chip developed for the AI workstation ELIS with the multiple programming paradigm language TAO. The objective of this microprocessor is to realize an S-expression machine that can match the speed of conventional machines for compiled code execution. Architectural features are a repetitive structure for VLSI implementation of the tagged architecture and a dedicated datapath for list manipulation. All the processor functions are realized on a single VLSI chip that uses a 2-micron CMOS process. ELIS supports not only LISP but also multiple programming paradigms. The ELIS interpreter has a higher performance than that of any other dedicated machine on the market.