著者

Neisei Hayashi Yosuke Mizuno Heeyoung Lee Kentaro Nakamura Sze Yun Set Shinji Yamashita

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE Electronics Express (ISSN:13492543)

巻号頁・発行日

vol.17, no.12, pp.20200139, 2020-06-25 (Released:2020-06-25)

参考文献数

39

被引用文献数

2 5

---

We present a method for generating cascaded forward Brillouin scattering (CFBS) on the basis of a counter-propagated pump-probe technique with backward stimulated Brillouin scattering used as its seed. The CFBS, induced by forward stimulated Brillouin scattering (FSBS), is generated via the energy transfer from the probe light to other acoustic resonance frequencies. The CFBS spectrum generated in a 390-m-long highly nonlinear fiber exhibits a high signal-to-noise ratio (SNR), and the center frequencies of its acoustic resonance peaks agree with theoretical values. In addition, the SNR dependence on pump/probe powers and the CFBS frequency shift dependence on temperature are investigated.

著者

Ryoya Hirata Toshihiko Hirooka Masato Yoshida Masataka Nakazawa

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE Electronics Express (ISSN:13492543)

巻号頁・発行日

vol.16, no.23, pp.20190664, 2019 (Released:2019-12-10)

参考文献数

30

被引用文献数

2 5

---

We present a wavelength-tunable ultrafast optical switch using a nonlinear optical loop mirror (NOLM), which has a low walk-off characteristic between the signal pulse and the control pulse thanks to the use of a dispersion-flattened highly nonlinear fiber. A 400-fs switching speed and an extinction ratio of >32 dB were obtained from 1528 to 1565 nm. The NOLM was applied to the 320 to 40 Gbaud demultiplexing of DQPSK Nyquist pulse signals, and error-free operation was achieved over the entire C-band.

著者

Masataka Motoyama Ken Umeno

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE Electronics Express (ISSN:13492543)

巻号頁・発行日

pp.18.20210011, (Released:2021-02-10)

参考文献数

32

---

This letter aims to demonstrate the concept of wireless power coloring (WPC), i.e., frequency division multiplexing of wireless power transfer (WPT). Currently, to obtain significant received power in WPT, the power is generated from a single transmission source. Herein, we propose a method of transmitting wireless power through more than one (N ≧ 2) multiplexed coloring source. To achieve this, we use power transmitting sources with different resonance frequencies in magnetic resonance-type WPT to selectively send power to a designated receiver.

著者

Takuya Hoshi Norihide Kashio Yuta Shiratori Kenji Kurishima Minoru Ida Hideaki Matsuzaki

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE Electronics Express (ISSN:13492543)

巻号頁・発行日

vol.16, no.3, pp.20181125, 2019 (Released:2019-02-10)

参考文献数

12

被引用文献数

2 6

---

This letter presents the current-gain and high-frequency characteristics of double heterojunction bipolar transistors (DHBTs) consisting of an n-InGaP emitter, a p-GaAsSb/p-InGaAsSb base, and an n-InP collector. The impact of the thickness of the first base metal (Pt) on the base contact resistivity is investigated in a p-GaAsSb/p-InGaAsSb test structure for the purpose of improving fmax. A low base contact resistivity (4.8 Ωµm2) is obtained when the Pt layer is thinner than the p-GaAsSb layer. A fabricated InGaP/GaAsSb/InGaAsSb DHBT with a 0.25-µm emitter exhibits a high current gain of 33 even though the base sheet resistance is as low as 1025 Ω/sq. The DHBT also exhibits an fmax of 703 GHz and a breakdown voltage of 5.4 V. These results demonstrate that this DHBT technology is useful for fabricating high-speed integrated circuits with high output voltages.

著者

Joonho Kong Kwangho Lee

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE Electronics Express (ISSN:13492543)

巻号頁・発行日

vol.14, no.11, pp.20170324, 2017 (Released:2017-06-10)

参考文献数

23

被引用文献数

3

---

Multiple clock domains mobile SoCs typically adopt dynamic voltage and frequency scaling (DVFS) for flexible power/energy management. However, adoption of system-level cache under DVFS-enabled CPU may incur abnormal cache hierarchy (i.e., a delay reversal between the high-level and low-level caches). It may lead to performance- and energy-inefficiency due to slower data delivery and meaningless accesses to intermediate levels of caches. To resolve this problem, we propose a DVFS-aware cache bypassing technique. Our technique profiles latencies of the various levels of the caches. Based on the profiled information, our technique adaptively bypasses intermediate levels of caches in the case of abnormal cache hierarchy and applies power-gating to that cache memory for better energy efficiency. According to our evaluation, our technique reduces L2 and system-level cache energy consumption by up to 14.5% while improving performance by up to 0.13% compared to the baseline.

著者

Zawawi Ruhaifi Abdullah Zulkifli Tun Zainal Azni

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE Electronics Express (ISSN:13492543)

巻号頁・発行日

vol.11, no.12, pp.20140383, 2014

被引用文献数

1

---

A new CMOS bandgap voltage reference (BGR) is proposed and simulated using Silterra 0.13 µm CMOS technology. The proposed BGR utilizes 3 curvature-corrected current generators that compensate for the output voltage variation in an extended temperature range. The proposed circuit generates an output voltage of 1.181 V with a variation of 380 µV from −50 °C to 150 °C.

著者

Zawawi Ruhaifi Abdullah Sidek Othman Hassin Wan Mohd Hafizi Wan Zulkipli Mohamad Izat Amir Rhaffor Nuha

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE Electronics Express (ISSN:13492543)

巻号頁・発行日

vol.8, no.22, pp.1876-1881, 2011

被引用文献数

5

---

In the current paper, an improvement of piecewise curvature-corrected CMOS bandgap reference (BGR) circuit is proposed. The circuit utilizes piecewise nonlinear curvature-corrected current (PNCCC) in a conventional BGR with a current control circuit, which compensates for the voltage reference at a higher temperature range. The current control circuit (CCC) is used to reduce the total current at low temperature when the PNCCC generator is inactive. The proposed circuit is realized in CMOS 0.13µm and has been verified to be able to save power consumption by 18.6% compared with a circuit without the current control circuit.

著者

Zawawi Ruhaifi Abdullah Sidek Othman

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE Electronics Express (ISSN:13492543)

巻号頁・発行日

vol.9, no.4, pp.240-244, 2012

被引用文献数

10

---

The current paper presents an improved bandgap voltage reference (BGR) that utilizes curvature-corrected current generators which compensate for the voltage reference at lower and higher temperature range. The voltage reference is operated with a supply voltage of 2.5V to achieve an output reference of 1.1835V. The temperature coefficient achieved from the circuit is 1.342ppm/°C, resulting from temperature changes between -50°C to 125°C, sixfold improvement from first-order BGR. The proposed circuit is simulated using Silterra 0.13µm CMOS technology.

著者

Masaya Ohta Atsuo Iwase Katsumi Yamashita

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE Electronics Express (ISSN:13492543)

巻号頁・発行日

vol.7, no.18, pp.1354-1358, 2010 (Released:2010-09-25)

参考文献数

7

被引用文献数

4 6

---

N-continuous OFDM is a modulation technique that has a lower sidelobe than the original OFDM as a result of the continuous connection with its higher-order derivatives between the OFDM symbols. However, N-continuous OFDM has a high symbol error rate. In the present paper, we improve N-continuous OFDM without increasing the symbol error rate by using a selected mapping technique.

著者

Lee Hu-ung Lee Seongjing Kim Jae-woon Won Youjip

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE Electronics Express (ISSN:13492543)

巻号頁・発行日

vol.12, no.12, pp.20150371-20150371, 2015

被引用文献数

3

---

In this paper, we propose the parallel architecture for high speed calculations of SHA-1, a widely used cryptographic hash function. Parallel SHA-1 consists of a number of base modules which process the message digest in parallel manner. The base module uses state of art SHA-1 acceleration techniques: loop unfolding, pre-processing, and pipelining. We achieved the performance improvement of 5.8% over the pipeline architecture that is known to have nearly achieved the theoretical performance limit. We implemented our system on the Xilinx Virtex-6 FPGA and verified the operations by interfacing it with MicroBlaze soft processor core.

著者

Takeshi Fujino Takaya Kubota Mitsuru Shiozaki

出版者

一般社団法人 電子情報通信学会

雑誌

IEICE Electronics Express (ISSN:13492543)

巻号頁・発行日

vol.14, no.2, pp.20162004-20162004, 2017 (Released:2017-01-25)

参考文献数

20

被引用文献数

5

---

Cryptosystems are widely used for achieving data confidentiality and authenticated access control. Recent cryptographic algorithms such as AES or RSA are computationally safe in the sense that it is practically impossible to reveal key information from a pair of plain and cipher texts if a key of sufficient length is used. A malicious attacker aims to reveal a key by exploiting implementation flaws in cryptographic modules. Even if there are no flaws in the software, the attacker will try to extract a secret key stored in the security hardware. The side-channel attacks (SCAs) are low cost and powerful against cryptographic hardware. The attacker exploits side-channel information such as power or electro-magnetic emission traces on the cryptographic circuits. In this paper, we will introduce the principle of SCAs and the countermeasures against SCAs.

著者

S. S. Gupta R. Senani

出版者

一般社団法人 電子情報通信学会

雑誌

IEICE Electronics Express (ISSN:13492543)

巻号頁・発行日

vol.1, no.16, pp.507-512, 2004 (Released:2004-11-25)

参考文献数

15

被引用文献数

10 14

---

Recently, the authors introduced two new second-order single-resistance-controlled oscillators (SRCO) employing four/three unity-gain cells (unity-gain voltage followers and unity-gain current followers). In this communication, a novel family of SRCOs has been presented which employ a reduced number of (only two) unity-gain cells as active elements. The workability of the new circuits has been confirmed by the SPICE simulations of their CMOS-implementable versions.

著者

Naoki Shinohara

出版者

一般社団法人 電子情報通信学会

雑誌

IEICE Electronics Express (ISSN:13492543)

巻号頁・発行日

vol.10, no.21, pp.20132009-20132009, 2013-11-10 (Released:2013-11-10)

参考文献数

53

被引用文献数

2 39 1

---

Microwave power transmission (MPT) has had a long history before the more recent movement toward wireless power transmission (WPT). MPT can be applied not only to beam-type point-to-point WPT but also to an energy harvesting system fed from distributed or broadcasting radio waves. The key technology is the use of a rectenna, or rectifying antenna, to convert a microwave signal to a DC signal with high efficiency. In this paper, various rectennas suitable for MPT are discussed, including various rectifying circuits, frequency rectennas, and power rectennas.

著者

Jung-Dong Park

出版者

一般社団法人 電子情報通信学会

雑誌

IEICE Electronics Express (ISSN:13492543)

巻号頁・発行日

vol.11, no.18, pp.20140806-20140806, 2014 (Released:2014-09-25)

参考文献数

6

被引用文献数

1

---

Switching mode CMOS frequency multipliers are studied in sub-Terahertz regime. Analysis on the multiplier architectures and optimal gate bias at CMOS switch are investigated to maximize output power at designated harmonics. Utilizing a differential pair, a 195 GHz tripler having a hair-pin filter is designed to maximize 3rd harmonics with −14.8 dB of conversion gain (CG) from Pin = +13 dBm of the balanced input, while the 260 GHz quadrupler utilizes quadruple-push pairs which achieves CG = −16 dB from two +13 dBm of the balanced I/Q driving signals in a 65 nm digital CMOS process.

著者

Jung-Dong Park

出版者

一般社団法人 電子情報通信学会

雑誌

IEICE Electronics Express (ISSN:13492543)

巻号頁・発行日

pp.11.20140806, (Released:2014-09-03)

参考文献数

6

被引用文献数

1

---

Switching mode CMOS frequency multipliers are studied in sub-Terahertz regime. Analysis on the multiplier architectures and optimal gate bias at CMOS switch are investigated to maximize output power at designated harmonics. Utilizing a differential pair, a 195GHz tripler having a hair-pin filter is designed to maximize 3rd harmonics with -14.8dB of conversion gain (CG) from Pin=+13dBm of the balanced input, while the 260GHz quadrupler utilizes quadruple-push pairs which achieves CG=-16dB from two +13dBm of the balanced I/Q driving signals in a 65nm digital CMOS process.

著者

Xuan Zhu Chunqing Wu Yuhua Tang Junjie Wu Xun Yi

出版者

一般社団法人 電子情報通信学会

雑誌

IEICE Electronics Express (ISSN:13492543)

巻号頁・発行日

vol.10, no.5, pp.20130013-20130013, 2013-03-05 (Released:2013-03-05)

参考文献数

8

被引用文献数

4

---

Utilizing memristor to obtain multi-level memory in nano-crossbar is a promising approach to enhance the memory density. In this paper, we proposed a solution for multi-level programming of memristor in nanocrossbar, which can be implemented on nanocrossbar without the need for extra selective devices. Meanwhile, using a general device model, this solution is demonstrated to be adaptive to a wide range of memristors that have been experimentally fabricated through HSPICE simulation.

著者

Son Trinh-Van Gina Kwon Keum Cheol Hwang Yong Bae Park

出版者

一般社団法人 電子情報通信学会

雑誌

IEICE Electronics Express (ISSN:13492543)

巻号頁・発行日

vol.10, no.17, pp.20130596-20130596, 2013-09-10 (Released:2013-09-10)

参考文献数

9

被引用文献数

1

---

A uniplanar, compact electromagnetic band-gap (UC-EBG) structure based on modified semi-Spidron fractal and meander-line strip (SFM-EBG) patterning is proposed. The semi-Spidron fractal geometry significantly increases the equivalent capacitance, whereas meander-line strips increase the equivalent inductance; as a result, the proposed design can be used to successfully miniaturize an EBG structure having a wide operating bandwidth. The measurement results show that a center frequency reduction of 32.14% as compared to that achieved by a conventional UC-EBG structure can be achieved by utilizing this proposed structure. The SFM-EBG structure has a measured operating bandwidth of 39.7% (3.33-4.98GHz), which is wider than that of a conventional UC-EBG (31%).

著者

Abe Shin-ya Shi Youhua Yanagisawa Masao Togawa Nozomu

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE Electronics Express (ISSN:13492543)

巻号頁・発行日

vol.9, no.17, pp.1414-1422, 2012

被引用文献数

14

---

In this paper, we propose multiple-supply-voltages aware high-level synthesis algorithm for <i>HDR architectures</i> which realizes high-speed and high-efficient circuits. We propose three new techniques: <i>virtual area estimation</i>, <i>virtual area adaptation</i>, and <i>floor-planning-directed huddling</i>, and integrate them into our HDR architecture synthesis algorithm. Virtual area estimation/adaptation effectively estimates a huddle area by gradually reducing it during iterations, which improves the convergence of our algorithm. Floorplanning-directed huddling determines huddle composition very effectively by performing floorplanning and functional unit assignment inside huddles simultaneously. Experimental results show that our algorithm achieves about 29% run-time-saving compared with the conventional algorithms, and obtains a solution which cannot be obtained by our original algorithm even if a very tight clock constraint is given.

著者

Phankong Nathabhat Funaki Tsuyoshi Hikihara Takashi

出版者

IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

雑誌

IEICE ELECTRONICS EXPRESS (ISSN:13492543)

巻号頁・発行日

vol.7, no.14, pp.1051-1057, 2010

被引用文献数

3

著者

Keun-Chang Kwak

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE Electronics Express (ISSN:13492543)

巻号頁・発行日

vol.6, no.4, pp.187-192, 2009 (Released:2009-02-25)

参考文献数

6

被引用文献数

1

---

This paper is concerned with real-time incremental face recognition for home service robots. For this purpose, we use an Incremental Tensor Subspace Analysis (ITSA) to enroll and recognize the user's face through low-price robot camera when robot performs the real-time customized service in home environments. Furthermore, we perform face recognition based on face database constructed in u-robot test bed environments in ETRI (Electronics and Telecommunications Research Institute). Thus it can be used as a core technique in conjunction with Human-Robot Interaction (HRI) that can naturally interact between human and robots in home robot applications. The experimental results on face database reveal that the presented method shows a good performance in comparison with the well-known methods in distant-varying environments.