著者

Yuki YAMANASHI Shohei NISHIMOTO Nobuyuki YOSHIKAWA

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Electronics (ISSN:09168516)

巻号頁・発行日

vol.E99-C, no.6, pp.692-696, 2016-06-01

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A single-flux-quantum (SFQ) arithmetic logic unit (ALU) was designed and tested to evaluate the effectiveness of introducing dynamically reconfigurable logic gates in the design of a superconducting logic circuit. We designed and tested a bit-serial SFQ ALU that can perform six arithmetic/logic functions by using a dynamically reconfigurable AND/OR gate. To ensure stable operation of the ALU, we improved the operating margin of the SFQ AND/OR gate by employing a partially shielded structure where the circuit is partially surrounded by under- and over-ground layers to reduce parasitic inductances. Owing to the introduction of the partially shielded structure, the operating margin of the dynamically reconfigurable AND/OR gate can be improved without increasing the circuit area. This ALU can be designed with a smaller circuit area compared with the conventional ALU by using the dynamically reconfigurable AND/OR gate. We implemented the SFQ ALU using the AIST 2.5kA/cm2 Nb standard process 2. We confirmed high-speed operation and correct reconfiguration of the SFQ ALU by a high-speed test. The measured maximum operation frequency was 30GHz.

著者

Shuping ZHANG Jinjia ZHOU Dajiang ZHOU Shinji KIMURA Satoshi GOTO

出版者

一般社団法人 電子情報通信学会

雑誌

IEICE Transactions on Electronics (ISSN:09168524)

巻号頁・発行日

vol.E100.C, no.3, pp.223-231, 2017-03-01 (Released:2017-03-01)

参考文献数

31

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In this paper, a hamburger architecture with a 3D stacked reconfigurable memory is proposed for a 4K motion estimation (ME) processor. By positioning the memory dies on both the top and bottom sides of the processor die, the proposed hamburger architecture can reduce the usage of the signal through-silicon via (TSV), and balance the power delivery network and the clock tree of the entire system. It results in 1/3 reduction of the usage of signal TSVs. Moreover, a stacked reconfigurable memory architecture is proposed to reduce the fabrication complexity and further reduce the number of signal TSVs by more than 1/2. The reduction of signal TSVs in the entire design is 71.24%. Finally, we address unique issues that occur in electronic design automation (EDA) tools during 3D large-scale integration (LSI) designs. As a result, a 4K ME processor with 7-die stacking 3D system-on-chip design is implemented. The proposed design can support real time 3840 × 2160 @ 120 fps encoding at 130 MHz with less than 540 mW.

著者

Naoki OYAMA Sho KANEKO Katsuaki MOMIYAMA Fumihiko HIROSE

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Electronics (ISSN:09168516)

巻号頁・発行日

vol.E94-C, no.12, pp.1838-1844, 2011-12-01

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Current density-voltage (J-V) and capacitance-voltage (C-V) characteristics of P3HT/n--silicon heterojunction diodes were investigated to clarify the carrier conduction mechanism at the organic/inorganic heterojunction. The J-V characteristics of the P3HT/n--Si junctions can be explained by a Schottky diode model with an interfacial layer. Diode parameters such as Schottky barrier height and ideality factor were estimated to be 0.78 eV and 3.2, respectively. The C-V analysis suggests that the depletion layer appears in the n--Si layer with a thickness of 1.2 µm from the junction with zero bias and the diffusion potential was estimated at 0.40 eV at the open-circuit condition. The present heterojunction allows a photovoltaic operation with power conversion efficiencies up to 0.38% with a simulated solar light exposure of 100 mW/cm2. The forward bias current was enhanced by coating the Si surface with a SiC layer, where the ideality factor was improved to be the level of 1.451.50.

著者

Asada Kunihiro Akita Junichi

出版者

一般社団法人電子情報通信学会

雑誌

IEICE transactions on electronics (ISSN:09168524)

巻号頁・発行日

vol.78, no.4, pp.436-440, 1995-04-25

被引用文献数

7

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Some CMOS gates are topologically asymmetric in inputs, even though they are logically symmetric. It implies a possibility to reduce power consumption by optimizing signal assignment to the inputs. In this study we theoretically derive power consumption of 2-input NAND gate based on transition probability of input signals, with taking into account charging current due to an internal node. We also propose a signal assignment method to input terminals for reducing power consumption reduction by extending our method for large circuits, and demonstrate the effect of power consumption reduction by the present method.

著者

Hai Huy NGUYEN PHAM Shintaro HISATAKE Tadao NAGATSUMA

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Electronics (ISSN:09168516)

巻号頁・発行日

vol.E98-C, no.8, pp.866-872, 2015-08-01

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We demonstrate the characterization of a horn antenna in the full F-band (90 ∼ 140 GHz) based on far-field transformation from near-field electro-optic (EO) measurement. Our nonpolarimetric self-heterodyne EO sensing system enables us to simultaneously measure the spatial distribution of the amplitude and phase of the RF signal. Because free-running lasers are used to generate and detect the RF signal, our EO sensing system has wide frequency tunability. Owing to the stable and reliable amplitude and phase measurements with minimal field perturbation, the estimated far-field patterns agree well with those of the simulated results. We have evaluated the estimation errors of the 3-dB beamwidth and position of the first sidelobe. The largest standard error of the measurements was 1.1° for 3-dB beamwidth and 3.5° for the position of first sidelobe at frequency 90 GHz. Our EO sensing system can be used to characterize and evaluate terahertz antennas for indoor communication applications such as small-size slot array antennas.

著者

Ishibashi Koichiro Komiyaji Kunihiro Morita Sadayuki Aoto Toshiro Ikeda Shuji Asayama Kyoichiro Koike Atsuyosi Yamanaka Toshiaki Hashimoto Naotaka Iida Haruhito Kojima Fumio Motohashi Koichi Sasaki Katsuro

出版者

一般社団法人電子情報通信学会

雑誌

IEICE transactions on electronics (ISSN:09168524)

巻号頁・発行日

vol.77, no.5, pp.741-748, 1994-05-25

被引用文献数

26

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A 16-Mb CMOS SRAM using 0.4-μm CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm^2 is fabricated and an address access time of 12.5 ns has been achieved.

著者

UCHIDA Teiji MIKAMI Osamu

出版者

一般社団法人電子情報通信学会

雑誌

IEICE transactions on electronics (ISSN:09168524)

巻号頁・発行日

vol.80, no.1, pp.81-87, 1997-01-25

参考文献数

13

被引用文献数

34

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Optical surface mount technology (O-SMT), which was proposed to provide a possible solution to growing serious problems in manufacturing process of optoelectronic products, is introduced. After discussing the basic idea of O-SMT, experimental results are also described to show its feasibility.

著者

Md. Mottaleb HOSSAIN Md. Abdullah-AL HUMAYUN Md. Tanvir HASAN Ashraful Ghani BHUIYAN Akihiro HASHIMOTO Akio YAMAMOTO

出版者

一般社団法人 電子情報通信学会

雑誌

IEICE Transactions on Electronics (ISSN:09168524)

巻号頁・発行日

vol.E95.C, no.2, pp.255-261, 2012-02-01 (Released:2012-02-01)

参考文献数

26

被引用文献数

2 9

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This paper reports on a theoretical study and modeling of a 1.55µm quantum dot heterostructure laser using InN as a promising candidate for the first time. Details of design and theoretical analysis of probability distribution of the optical transition energy, threshold current density, modal gain, and differential quantum efficiency are presented considering a single layer of quantum dots. Dependence of threshold current density on the RMS value of quantum dot size fluctuations and the cavity length is studied. A low threshold current density of ∼51Acm-2 is achieved at room temperature for a cavity length of 640µm. An external differential efficiency of ∼65% and a modal gain of ∼12.5cm-1 are obtained for the proposed structure. The results indicate that the InN based quantum dot laser is a promising one for the optical communication system.

著者

Sang-Keun HAN KeeChan PARK Young-Hyun JUN Bai-Sun KONG

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Electronics (ISSN:09168516)

巻号頁・発行日

vol.E95-C, no.11, pp.1824-1826, 2012-11-01

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This paper introduces novel high-speed and low-power boosted level converters for use in dual-supply systems. The proposed level converters adopt a voltage boosting at the gate of pull-down transistors to improve driving speed and reduce contention problem. Comparison results in a 0.13-µm CMOS process indicated that the proposed level converters provided up to 70% delay reduction with up to 57% power-delay product (PDP) reduction as compared to conventional level converters.

著者

AKIMA Hisanao SATO Shigeo NAKAJIMA Koji

出版者

一般社団法人電子情報通信学会

雑誌

IEICE transactions on electronics (ISSN:09168524)

巻号頁・発行日

vol.87, no.5, pp.832-834, 2004-05-01

被引用文献数

1

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A random number generator composed of single electron devices is presented. Due to stochastic behavior of electron tunneling process, single electron devices have intrinsic randomness. Using its randomness, a true random number generator can be implemented. Although fluctuation of device parameters degrades the performance of the proposed circuit, we show that the adjustment of the bias voltages can compensate the fluctuation.

著者

Hyungjin KIM Min-Chul SUN Hyun Woo KIM Sang Wan KIM Garam KIM Byung-Gook PARK

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Electronics (ISSN:09168516)

巻号頁・発行日

vol.E95-C, no.5, pp.820-825, 2012-05-01

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Although the Tunnel Field-Effect Transistor (TFET) is a promising device for ultra-low power CMOS technology due to the ability to reduce power supply voltage and very small off-current, there have been few reports on the control of VT for TFETs. Unfortunately, the TFET needs a different technique to adjust VT than the MOSFET by channel doping because most of TFETs are fabricated on SOI substrates. In this paper, we propose a technique to control VT of the TFET by putting an additional VT-control doping region (VDR) between source and channel. We examine how much VT is changed by doping concentration of VDR. The change of doping concentration modulates VT because it changes the semiconductor work function difference, ψs,channel-ψs,source, at off-state. Also, the effect of the size of VDR is investigated. The region can be confined to the silicon surface because most of tunneling occurs at the surface. At the same time, we study the optimum width of this region while considering the mobility degradation by doping. Finally, the effect of the SOI thickness on the VDR adjusted VT of TFET is also investigated.

著者

Zhisheng LI Johan BAUWELINCK Guy TORFS Xin YIN Jan VANDEWEGE

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Electronics (ISSN:09168516)

巻号頁・発行日

vol.E95-C, no.4, pp.765-767, 2012-04-01

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This paper presents a new common-mode stabilization method for a CMOS differential cascode Class-E power amplifier with LC-tank based driver stage. The stabilization method is based on the identification of the poles and zeros of the closed-loop transfer function at a critical node. By adding a series resistor at the common-gate node of the cascode transistor, the right-half-plane poles are moved to the left half plane, improving the common-mode stability. The simulation results show that the new method is an effective way to stabilize the PA.

著者

Yuki ATSUMI Manabu ODA Joonhyun KANG Nobuhiko NISHIYAMA Shigehisa ARAI

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Electronics (ISSN:09168516)

巻号頁・発行日

vol.E95-C, no.2, pp.229-236, 2012-02-01

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Photonic integrated circuits (PICs) produced by large-scale integration (LSI) on Si platforms have been intensively researched. Since thermal diffusion from the LSI logic layer is a serious obstacle to realizing a Si-based optical integrated circuit, we have proposed and realized athermal wavelength filters using Si slot waveguides embedded with benzocyclobutene (BCB). First, the athermal conditions were theoretically investigated by controlling the waveguide and gap width of the slot waveguides. In order to introduce the calculated waveguide structures to wavelength filters, the propagation losses and bending losses of the Si slot waveguides were evaluated. The propagation losses were measured to be 5.6 and 5.3 dB/cm for slot waveguide widths of 500 and 700 nm, respectively. Finally, athermal wavelength filters, a ring resonator, and a Mach-Zhender interferometer (MZI) with a slot waveguide width of 700 nm were designed and fabricated. Further, a temperature coefficient of -0.9 pm/K for the operating wavelength was achieved with the athermal MZI.

著者

Masahiro FUNAHASHI Fapei ZHANG Nobuyuki TAMAOKI

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Electronics (ISSN:09168516)

巻号頁・発行日

vol.E94-C, no.11, pp.1720-1726, 2011-11-01

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Thin-film transistors based on Liquid-crystalline phenylterthiophenes, 3-TTPPh-5 and 3-TTPPhF4-6 are fabricated with a spin-coating method. The devices exhibit p-type operation with the mobility on the order of 10-2 cm2V-1s-1. The field-effect mobilities of the transistors using 3-TTPPh-5 and 3-TTPPhF4-6 are almost independent of the temperature above room temperature. In particular, the temperature range in which the mobility is constant is between 230 and 350 K for 3-TTPPh-5.

著者

LI Keren

出版者

一般社団法人電子情報通信学会

雑誌

IEICE transactions on electronics (ISSN:09168524)

巻号頁・発行日

vol.81, no.12, pp.1845-1851, 1998-12-25

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In this paper, we present an analysis of the microstrip lines whose strip conductors are of various cross-sections, such as rectangular cross-section, triangle cross-section, and half-cycle cross-section. The method employed is the boundary integral equation method (BIEM). Numerical results for these microstrip lines demonstrate various shape effects of the strip conductor on the characteristics of lines. The processing technique on the convergence of the Green's function is also described.

著者

OHTSUKI Masaaki KAWAI Masato FUKUI Masahiro

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE transactions on electronics (ISSN:09168524)

巻号頁・発行日

vol.92, no.4, pp.500-507, 2009-04-01

被引用文献数

4 5

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Accompanying with the popularization of portable equipments, and the rapid growth of the size of the electric systems, efficient low power design methodologies have been highly required. To satisfy these requests, a high accurate and high efficient power analysis in higher abstraction level is very important. The design environment is composed by efficient algorithms of power modeling, power library building, and data extracting. Those components of the environment should be balanced for the total efficiency and accuracy. We have proposed a new efficient power modeling environment which uses a look-up table (LUT). It reduces the size of the LUT drastically, compared to conventional algorithms. It makes the power analysis and library building high efficient. The experimental results show that our approach reduces the computation time to build the library to one tenth while keeping the accuracy of the power analysis. The RMS error and the largest error has been less than 8.30%, 59.16%, respectively.

著者

HANYU Takahiro KAMEYAMA Michitaka

出版者

一般社団法人電子情報通信学会

雑誌

IEICE transactions on electronics (ISSN:09168524)

巻号頁・発行日

vol.82, no.9, pp.1662-1668, 1999-09-25

被引用文献数

12

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A new logic-in-memory VLSI architecture based on multiple-valued floating-gate-MOS pass-transistor logic is proposed to solve the communication bottleneck between memory and logic modules. Multiple-valued stored data are represented by the threshold voltage of a floating-gate MOS transistor, so that a single floating-gate MOS transistor is effectively employed to merge multiple-valued threshold-literal and pass-switch functions. As an application, a four-valued logicin-memory VLSI for high-speed pattern recognition is also presented. The proposed VLSI detects a stored reference word with the minimum Manhattan distance between a 16-bit input word and 16-bit stored reference words. The effective chip area, the switching delay and the power dissipation of a new four-valued full adder, which is a key component of the proposed logic-in-memory VLSI, are reduced to about 33 percent, 67 percent and 24 percent, respectively, in comparison with those of the corresponding binary CMOS implementation under a 0.5-μm flash EEPROM, technology.