著者

筧 康明

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

電子情報通信学会論文誌 D (ISSN:18804535)

巻号頁・発行日

vol.J94-D, no.1, pp.3-11, 2011-01-01

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近年のインターネット環境の発展に伴い,より自由な表現が可能になったことで,新たなWeb環境とのかかわり方を設計することが重要となってきている.特に,実世界とWeb世界の乖離を解消するために,実世界とのつながりや,他のユーザとの緩やかなつながりを提供することが重要な課題とされる.このために,本研究では,(1) Web上のアクティビティの視覚化,(2)実世界情報の取得と視覚化,(3)実世界と関連づけた情報提示の三つの要素をアプリケーション上に付与し,実世界指向Webアプリケーションを提案する.本論文では,Webと実世界をつなぐ試みとしてこれまでの筆者らの試みを紹介するとともに,それらの運用を通した考察を行う.

著者

中田 篤志 角 康之 西田 豊明

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

電子情報通信学会論文誌 D (ISSN:18804535)

巻号頁・発行日

vol.J94-D, no.1, pp.113-123, 2011-01-01

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我々は会話中に,視線,指差し,うなずきといった様々な非言語行動を行っている.それらの非言語行動は会話の制御に使われていると考えられ,その出現パターンには一定の構造がある.本研究ではこれを会話構造と呼ぶ.本研究では,会話参加者らによる非言語行動出現の時間構造をN-gramで表現し,会話記録のデータから会話構造を自動抽出するインタラクションマイニングの手法を提案する.そして,提案手法を用いてポスター発表会話とポスター環境自由会話という2種類の会話状況における会話構造の自動抽出を試みた.その結果,発話者は非発話者より指差しが多い,とか,うなずきの後に相槌を行うことが多いといった会話構造は二つの会話状況に共通して見られる一方で,沈黙の後に発話を続けるのは元の発話者であるという会話構造はポスター発表会話特有のものであるといったことを確認することができた.

著者

西本 卓也 渡辺 隆行

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

電子情報通信学会論文誌 D (ISSN:18804535)

巻号頁・発行日

vol.J94-D, no.1, pp.209-220, 2011-01-01

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視覚障害者のコンピュータ利用に適した超早口音声の音質を改善することが望まれている.しかし超早口音声の評価のためには,聞き手の慣れの効果の考慮が重要である.本研究では親密度を統制した超早口音声の聴取において(1)実験の途中での親密度条件の変化,(2)親密度に関する教示の有無,の要因が聞き手の課題への慣れに与える影響を検証した.約21モーラ/秒という超早口音声の聴取における了解度と心的負荷に着目した実験から,「慣れによって親密度が高いという自覚が促された場合に,特にトップダウン情報としての心的辞書へのアクセスが促進され,その結果として了解度が高くなり心的負荷が少なくなる」という仮説を支持する結果が得られた.

著者

國信 茂太 半田 恵一 佐々木 康 飯窪 孝

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

電子情報通信学会論文誌 D (ISSN:18804535)

巻号頁・発行日

vol.J94-D, no.1, pp.312-323, 2011-01-01

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ノートPCのきょう体内に様々な配置制約をもつ部品をコンパクトに配置するための配置案を算出するシステムを提案する.提案する部品配置設計システムは,与えられた幅・奥行でできるだけ厚みの薄い配置案を算出する.提案システムには,開発コストや重さ等に影響するメイン基板のサイズを小さくする機能がある.また,設計者に選択の幅を残すため,複数の配置案を算出する.提案システムでは,PCのきょう体は五つの配置層(二次元平面)から構成されると考え,部品は,まず鉛直方向の配置位置制約に対応した配置層に,配置制約及び配置要求を考慮して配置される.配置層への部品配置は二次元平面上の配置位置を決めることに対応する.そして,配置層に配置された部品を三次元に集積することで三次元の部品配置案を得る.実験の結果,部品数が54の高機能・多機能AVノートPCの場合,約200秒で実際のPC設計者が入力する許容最大厚みを下回る配置案が10程度得られることを確認した.

著者

後藤 敏行 田村 直良 立野 玲子

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

電子情報通信学会論文誌 D (ISSN:18804535)

巻号頁・発行日

vol.J93-D, no.10, pp.1947-1957, 2010-10-01

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電子楽譜の普及によりインターネットを経由して楽譜情報にアクセスできる環境が整ってきた.これに対して,視覚障害者が用いる点字楽譜はいまだ入手が困難である.筆者らは,電子楽譜( MusicXML )から点字楽譜を生成する自動翻訳システムを研究開発し,ホームページで公開するとともに,システムの評価と拡張を進めてきた.本研究では,交響曲などを含めた多様な楽譜に対応し,点字楽譜における短縮表現などの多様な表現形式を取捨選択できるように自動翻訳手法の機能拡張を行うとともに,インターネット上の電子楽譜を翻訳して提供する機能を開発した.本論文では,これらの機能と利用状況から示されたシステムの有用性について報告する.

著者

井上 中順 斉藤 辰彦 篠田 浩一 古井 貞煕

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

電子情報通信学会論文誌 D (ISSN:18804535)

巻号頁・発行日

vol.J93-D, no.12, pp.2633-2644, 2010-12-01

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本研究では,映像の中から「飛行機」や「歌っている人」といった高次特徴を検出するタスクに対し,SIFT特徴とMFCC特徴の混合ガウス分布(GMM)を用いた統計的手法を提案する.検出手法には,話者認識などで用いられてきたゆう度比による検出と,GMM Supervector SVM (GS-SVM)による検出の二つを用いる.ゆう度比による検出では,高次特徴が出現する部分としない部分のGMMをそれぞれ学習し,二つのモデルから得られるゆう度の比をもとに高次特徴を検出する.GS-SVMでは,各ショットに対するGMMを求め,GMM間の距離から定義されるRBFカーネルを用いたSVMで学習・識別を行う.最後に,各手法から対数ゆう度比を求め,その重み付き和により手法の融合を行う.TRECVID2009のデータセットを用いて評価実験を行った結果,Mean Average PrecisionはSIFT特徴とGS-SVMを用いた場合の0.141から,融合手法により0.173まで向上した.

著者

Yuki ANDO Seiya SHIBATA Shinya HONDA Hiroyuki TOMIYAMA Hiroaki TAKADA

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences (ISSN:09168508)

巻号頁・発行日

vol.E93-A, no.12, pp.2509-2516, 2010-12-01

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We present a hardware sharing method for design space exploration of multi-processor embedded systems. In our prior work, we had developed a system-level design tool named SystemBuilder which automatically synthesizes target implementation of a system from a functional description. In this work, we have extended SystemBuilder so that it can automatically synthesize an area-efficient implementation which shares a hardware module among different applications. With SystemBuilder, designers only need to enable an option in order to share a hardware module. The designers, therefore, can easily explore a design space including hardware sharing in short time. A case study shows the effectiveness of the hardware sharing on design space exploration.

著者

Tohru ISHIHARA

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences (ISSN:09168508)

巻号頁・発行日

vol.E93-A, no.12, pp.2533-2541, 2010-12-01

被引用文献数

5

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This paper proposes an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The processor consists of multiple PE (processing element) cores and a selective set-associative cache memory. The PE-cores have the same instruction set architecture but differ in their clock speeds and energy consumptions. Only a single PE-core is activated at a time and the other PE-cores are deactivated using clock gating and signal gating techniques. The major advantage over the DVS processors is a small overhead for changing its performance. The gate-level simulation demonstrates that our processor can change its performance within 1.5 microsecond and dissipates about 10 nano-joule while conventional DVS processors need hundreds of microseconds and dissipate a few micro-joule for the performance transition. This makes it possible to apply our multi-performance processor to many real-time systems and to perform finer grained and more sophisticated dynamic voltage control.

著者

Makoto SUGIHARA

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences (ISSN:09168508)

巻号頁・発行日

vol.E93-A, no.12, pp.2560-2569, 2010-12-01

被引用文献数

2

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Utilizing a heterogeneous multiprocessor system has become a popular design paradigm to build an embedded system at a cheap cost. A reliability issue, which is vulnerability to soft errors, has not been taken into account in the conventional IC (integrated circuit) design flow, while chip area, performance, and power consumption have been done. This paper presents a system design paradigm in which a heterogeneous multiprocessor system is synthesized and its chip area is minimized under real-time and reliability constraints. First we define an SEU vulnerability factor as a vulnerability measure for computer systems so that we evaluate task-wise reliability over various processor structures. Next we build a mixed integer linear programming (MILP) model for minimizing the chip area of a heterogeneous multiprocessor system under real-time and SEU vulnerability constraints. Finally, we show several experimental results on our synthesis approach. Experimental results show that our design paradigm has achieved automatic generation of cost-competitive and reliable heterogeneous multiprocessor systems.

著者

Hasitha Muthumala WAIDYASOORIYA Daisuke OKUMURA Masanori HARIYAMA Michitaka KAMEYAMA

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences (ISSN:09168508)

巻号頁・発行日

vol.E93-A, no.12, pp.2570-2580, 2010-12-01

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Heterogeneous multi-core processors are attracted by the media processing applications due to their capability of drawing strengths of different cores to improve the overall performance. However, the data transfer bottlenecks and limitations in the task allocation due to the accelerator-incompatible operations prevents us from gaining full potential of the heterogeneous multi-core processors. This paper presents a task allocation method based on algorithm transformation to increase the freedom of task allocation. We use approximation methods such as CORDIC algorithms to map the accelerator-incompatible operations to accelerator cores. According to the experimental results using HOG descriptor computation, the proposed task allocation method reduces the data transfer time by more than 82% and the total processing time by more than 79% compared to the conventional task allocation method.

著者

Shinyu NINOMIYA Masanori HASHIMOTO

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences (ISSN:09168508)

巻号頁・発行日

vol.E93-A, no.12, pp.2441-2446, 2010-12-01

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Statistical timing analysis for manufacturing variability requires modeling of spatially-correlated variation. Common grid-based modeling for spatially-correlated variability involves a trade-off between accuracy and computational cost, especially for PCA (principal component analysis). This paper proposes to spatially interpolate variation coefficients for improving accuracy instead of fining spatial grids. Experimental results show that the spatial interpolation realizes a continuous expression of spatial correlation, and reduces the maximum error of timing estimates that originates from sparse spatial grids For attaining the same accuracy, the proposed interpolation reduced CPU time for PCA by 97.7% in a test case.

著者

Kentaro ISHIZU Homare MURAKAMI Stanislav FILIN Hiroshi HARADA

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Communications (ISSN:09168516)

巻号頁・発行日

vol.E93-B, no.12, pp.3311-3322, 2010-12-01

被引用文献数

4

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Selections of radio access networks by terminals are currently not coordinated and utilizations of the radio resources are not balanced. As a result, radio resources on some radio systems are occupied even though others can afford. In this paper, in order to provide a framework to resolve this issue, Cognitive Wireless Router (CWR) system is proposed for distributed management and independent reconfiguration of heterogeneous wireless networks. The proposed system selects appropriate operational frequency bands and radio systems to connect to the Internet in corporation between the CWRs and a server and therefore can provide optimized wireless Internet access easily even in environments without wired networks. The developed prototype system reconfigures the radio devices to connect to the Internet in 27 seconds at most. It is revealed that this reconfiguration time can be shortened to less than 100 ms by elaborating its procedure. It is also clarified that network data speed required at the server to deal with 10,000 CWRs is only 4.1 Mbps.

著者

Yi TANG Junchen JIANG Xiaofei WANG Chengchen HU Bin LIU Zhijia CHEN

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Information and Systems (ISSN:09168532)

巻号頁・発行日

vol.E93-D, no.12, pp.3232-3242, 2010-12-01

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Multi-pattern matching is a key technique for implementing network security applications such as Network Intrusion Detection/Protection Systems (NIDS/NIPSes) where every packet is inspected against tens of thousands of predefined attack signatures written in regular expressions (regexes). To this end, Deterministic Finite Automaton (DFA) is widely used for multi-regex matching, but existing DFA-based researches have claimed high throughput at an expense of extremely high memory cost, so fail to be employed in devices such as high-speed routers and embedded systems where the available memory is quite limited. In this paper, we propose a parallel architecture of DFA called Parallel DFA (PDFA) taking advantage of the large amount of concurrent flows to increase the throughput with nearly no extra memory cost. The basic idea is to selectively store the underlying DFA in memory modules that can be accessed in parallel. To explore its potential parallelism we intensively study DFA-split schemes from both state and transition points in this paper. The performance of our approach in both the average cases and the worst cases is analyzed, optimized and evaluated by numerical results. The evaluation shows that we obtain an average speedup of 100 times compared with traditional DFA-based matching approach.

著者

Tongsheng GENG Leibo LIU Shouyi YIN Min ZHU Shaojun WEI

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Information and Systems (ISSN:09168532)

巻号頁・発行日

vol.E93-D, no.12, pp.3223-3231, 2010-12-01

被引用文献数

6

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This paper proposes approaches to perform HW/SW (Hardware/Software) partition and parallelization of computing-intensive tasks of the H.264 HiP (High Profile) decoding algorithm on an embedded coarse-grained reconfigurable multimedia system, called REMUS (REconfigurable MUltimedia System). Several techniques, such as MB (Macro-Block) based parallelization, unfixed sub-block operation etc., are utilized to speed up the decoding process, satisfying the requirements of real-time and high quality H.264 applications. Tests show that the execution performance of MC (Motion Compensation), deblocking, and IDCT-IQ (Inverse Discrete Cosine Transform-Inverse Quantization) on REMUS is improved by 60%, 73%, 88.5% in the typical case and 60%, 69%, 88.5% in the worst case, respectively compared with that on XPP PACT (a commercial reconfigurable processor). Compared with ASIC solutions, the performance of MC is improved by 70%, 74% in the typical and in the worst case, respectively, while those of Deblocking remain the same. As for IDCT_IQ, the performance is improved by 17% no matter in the typical or worst case. Relying on the proposed techniques, 1080p@30 fps of H.264 HiP@ Level 4 decoding could be achieved on REMUS when utilizing a 200 MHz working frequency.

著者

Yoshiki YUNBE Masayuki MIYAMA Yoshio MATSUDA

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Information and Systems (ISSN:09168532)

巻号頁・発行日

vol.E93-D, no.12, pp.3284-3293, 2010-12-01

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This paper describes an affine motion estimation processor for real-time video segmentation. The processor estimates the dominant motion of a target region with affine parameters. The processor is based on the Pseudo-M-estimator algorithm. Introduction of an image division method and a binary weight method to the original algorithm reduces data traffic and hardware costs. A pixel sampling method is proposed that reduces the clock frequency by 50%. The pixel pipeline architecture and a frame overlap method double throughput. The processor was prototyped on an FPGA; its function and performance were subsequently verified. It was also implemented as an ASIC. The core size is 5.05.0 mm2 in 0.18 µm process, standard cell technology. The ASIC can accommodate a VGA 30 fps video with 120 MHz clock frequency.

著者

Xiaomin JIA Pingjing LU Caixia SUN Minxuan ZHANG

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Information and Systems (ISSN:09168532)

巻号頁・発行日

vol.E93-D, no.12, pp.3211-3222, 2010-12-01

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Chip Multi-Processors (CMPs) emerge as a mainstream architectural design alternative for high performance parallel and distributed computing. Last Level Cache (LLC) management is critical to CMPs because off-chip accesses often require a long latency. Due to its short access latency, well performance isolation and easy scalability, private cache is an attractive design alternative for LLC of CMPs. This paper proposes program Behavior Identification-based Cache Sharing (BICS) for LLC management. BICS is based on a private cache organization for the shorter access latency. Meanwhile, BICS tries to simulate a shared cache organization by allowing evicted blocks of one private LLC to be saved at peer LLCs. This technique is called spilling. BICS identifies cache behavior types of applications at runtime. When a cache block is evicted from a private LLC, cache behavior characteristics of the local application are evaluated so as to determine whether the block is to be spilled. Spilled blocks are allowed to replace some valid blocks of the peer LLCs as long as the interference is within a reasonable level. Experimental results using a full system CMP simulator show that BICS improves the overall throughput by as much as 14.5%, 12.6%, 11.0% and 11.7% (on average 8.8%, 4.8%, 4.0% and 6.8%) over private cache, shared cache, Utility-based Cache Partitioning (UCP) scheme and the baseline spilling-based organization Cooperative Caching (CC) respectively on a 4-core CMP for SPEC CPU2006 benchmarks.

著者

Min ZHU Leibo LIU Shouyi YIN Chongyong YIN Shaojun WEI

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Information and Systems (ISSN:09168532)

巻号頁・発行日

vol.E93-D, no.12, pp.3202-3210, 2010-12-01

被引用文献数

11

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This paper introduces a cycle-accurate Simulator for a dynamically REconfigurable MUlti-media System, called SimREMUS. SimREMUS can either be used at transaction-level, which allows the modeling and simulation of higher-level hardware and embedded software, or at register transfer level, if the dynamic system behavior is desired to be observed at signal level. Trade-offs among a set of criteria that are frequently used to characterize the design of a reconfigurable computing system, such as granularity, programmability, configurability as well as architecture of processing elements and route modules etc., can be quickly evaluated. Moreover, a complete tool chain for SimREMUS, including compiler and debugger, is developed. SimREMUS could simulate 270 k cycles per second for million gates SoC (System-on-a-Chip) and produced one H.264 1080p frame in 15 minutes, which might cost days on VCS (platform: CPU: E5200@ 2.5 Ghz, RAM: 2.0 GB). Simulation showed that 1080p@30 fps of H.264 High Profile@ Level 4 can be achieved when exploiting a 200 MHz working frequency on the VLSI architecture of REMUS.

著者

杉田 泰則 吉川 敏則 相川 直幸

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

電子情報通信学会論文誌 A (ISSN:09135707)

巻号頁・発行日

vol.J93-A, no.12, pp.795-804, 2010-12-01

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ディジタル信号処理の分野において,処理目的に応じてリアルタイムでフィルタ特性を変化させたいことがある.この要求を満たすために,使用時に周波数特性を容易に変えられる可変ディジタルフィルタに関する研究が近年盛んに行われている.本論文では,阻止域において部分的に大きい減衰量を複数もち,かつ,それら大きな減衰の領域がそれぞれ可変な低遅延FIRディジタルフィルタの設計法を提案する.提案法では,重み付き最小二乗法を用い,重み関数を更新して最小二乗問題を繰り返し解くことで準等リプル特性を得る.

著者

二宮 洋

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

電子情報通信学会論文誌 A (ISSN:09135707)

巻号頁・発行日

vol.J93-A, no.12, pp.828-832, 2010-12-01

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本研究では準ニュートン法に基づくニューラルネットワークの新たな学習法を提案する.従来,準ニュートン法はこう配法に基づく強力な収束特性をもつバッチ学習法であった.近年,大規模なデータを扱う問題への応用としてオンライン準ニュートン法が提案された.本研究ではオンライン準ニュートン法の学習データの与え方を改良することで,準ニュートン法の収束特性を向上させた学習法を提案する.

著者

峰村 今朝明 後藤 理 東山 三樹夫 白井 克彦

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

電子情報通信学会論文誌 A (ISSN:09135707)

巻号頁・発行日

vol.J93-A, no.12, pp.833-834, 2010-12-01

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単母音スペクトルのz変換表示からべき級数展開表現への拡張を検討した.単母音スペクトルはべき級数展開において周波数幅約120 (Hz)ごとに基点を置いた6次関数で表現できる.更にべき級数展開表現を用いた多項式の零点分布により,話者の違いを確認した.