著者

吉丸 克己 [ヨシマル カツミ]

出版者

龍南會

雑誌

龍南

巻号頁・発行日

vol.236, pp.30-46, 1937-02-16

著者

瀬川 裕司

出版者

明治大学教養論集刊行会

雑誌

明治大学教養論集 (ISSN:03896005)

巻号頁・発行日

no.354, pp.85-100, 2002-03

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オーストリアではじめて映画が有料公開されたのは、1896年3月27日、ウィーン一区ケルントナー通り49番地でのことである。パリのグラン・カフェでリュミエール兄弟がシネマトグラフを発表したのは、前年の12月だった。三ヶ月後、兄弟は自社の上映装置とフィルムをもたせて、部下のウジェーヌ・デュポンをウィーンに派遣した。上映は午前10時から夜の8時までノンストップでおこなわれた。料金は50クロイツェル、映写されたのは「パリのコンコルド広場」「鉄道」「海」等の今日でもよく知られている短編である。デュポンらはウィーン到着後、フランス大使館や各種教育機関等で何度も試写をおこなった末に、ようやくその場所での上映許可を得たのだった。

著者

横田 誠 斉藤 浩徳 武子 政信

雑誌

全国大会講演論文集

巻号頁・発行日

vol.54, pp.187-188, 1997-03-12

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パタン化された問題空間を入出力系とする情報的感性対応の人工的システムの進化過程を考えている。一般化パタン系は, 絵画パタン系と考えている。絵画的パタンは, 画素パタンの連鎖パタン系である。又, 絵画パタン系には, 額縁のような, 境界条件の設定の有, 無の系がある。絵画パタン系の基礎系として, 矩形画素の連鎖系である, 抽象画系, モンドリアンパタン系が考えられてている。今回は, 矩形額縁ワク内の矩形画素連鎖系に対して, アルキメデスに由来する, アルベロス円列, すなわち円形額緑ワク内の円形画素の連鎖系の基礎的系について考える。感受や, 変形等の感性対応の人工的システムを考える前提として, その入出カパタン系を線路系と考え, 数理的接続特性を考える必要がある。その上で, 表情とか, 説明・案内効果等を考えることになる。

著者

津田 和良 藤原 久子 山本 覚次

出版者

日本眼科紀要会

雑誌

日本眼科紀要 (ISSN:00155667)

巻号頁・発行日

vol.34, no.1, pp.p1-4, 1983-01

著者

Makoto SUGIHARA

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences (ISSN:09168508)

巻号頁・発行日

vol.E93-A, no.12, pp.2560-2569, 2010-12-01

被引用文献数

2

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Utilizing a heterogeneous multiprocessor system has become a popular design paradigm to build an embedded system at a cheap cost. A reliability issue, which is vulnerability to soft errors, has not been taken into account in the conventional IC (integrated circuit) design flow, while chip area, performance, and power consumption have been done. This paper presents a system design paradigm in which a heterogeneous multiprocessor system is synthesized and its chip area is minimized under real-time and reliability constraints. First we define an SEU vulnerability factor as a vulnerability measure for computer systems so that we evaluate task-wise reliability over various processor structures. Next we build a mixed integer linear programming (MILP) model for minimizing the chip area of a heterogeneous multiprocessor system under real-time and SEU vulnerability constraints. Finally, we show several experimental results on our synthesis approach. Experimental results show that our design paradigm has achieved automatic generation of cost-competitive and reliable heterogeneous multiprocessor systems.

著者

Yuki ANDO Seiya SHIBATA Shinya HONDA Hiroyuki TOMIYAMA Hiroaki TAKADA

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences (ISSN:09168508)

巻号頁・発行日

vol.E93-A, no.12, pp.2509-2516, 2010-12-01

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We present a hardware sharing method for design space exploration of multi-processor embedded systems. In our prior work, we had developed a system-level design tool named SystemBuilder which automatically synthesizes target implementation of a system from a functional description. In this work, we have extended SystemBuilder so that it can automatically synthesize an area-efficient implementation which shares a hardware module among different applications. With SystemBuilder, designers only need to enable an option in order to share a hardware module. The designers, therefore, can easily explore a design space including hardware sharing in short time. A case study shows the effectiveness of the hardware sharing on design space exploration.

著者

Tohru ISHIHARA

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences (ISSN:09168508)

巻号頁・発行日

vol.E93-A, no.12, pp.2533-2541, 2010-12-01

被引用文献数

5

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This paper proposes an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The processor consists of multiple PE (processing element) cores and a selective set-associative cache memory. The PE-cores have the same instruction set architecture but differ in their clock speeds and energy consumptions. Only a single PE-core is activated at a time and the other PE-cores are deactivated using clock gating and signal gating techniques. The major advantage over the DVS processors is a small overhead for changing its performance. The gate-level simulation demonstrates that our processor can change its performance within 1.5 microsecond and dissipates about 10 nano-joule while conventional DVS processors need hundreds of microseconds and dissipate a few micro-joule for the performance transition. This makes it possible to apply our multi-performance processor to many real-time systems and to perform finer grained and more sophisticated dynamic voltage control.

著者

Hasitha Muthumala WAIDYASOORIYA Daisuke OKUMURA Masanori HARIYAMA Michitaka KAMEYAMA

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences (ISSN:09168508)

巻号頁・発行日

vol.E93-A, no.12, pp.2570-2580, 2010-12-01

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Heterogeneous multi-core processors are attracted by the media processing applications due to their capability of drawing strengths of different cores to improve the overall performance. However, the data transfer bottlenecks and limitations in the task allocation due to the accelerator-incompatible operations prevents us from gaining full potential of the heterogeneous multi-core processors. This paper presents a task allocation method based on algorithm transformation to increase the freedom of task allocation. We use approximation methods such as CORDIC algorithms to map the accelerator-incompatible operations to accelerator cores. According to the experimental results using HOG descriptor computation, the proposed task allocation method reduces the data transfer time by more than 82% and the total processing time by more than 79% compared to the conventional task allocation method.

著者

Shinyu NINOMIYA Masanori HASHIMOTO

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences (ISSN:09168508)

巻号頁・発行日

vol.E93-A, no.12, pp.2441-2446, 2010-12-01

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Statistical timing analysis for manufacturing variability requires modeling of spatially-correlated variation. Common grid-based modeling for spatially-correlated variability involves a trade-off between accuracy and computational cost, especially for PCA (principal component analysis). This paper proposes to spatially interpolate variation coefficients for improving accuracy instead of fining spatial grids. Experimental results show that the spatial interpolation realizes a continuous expression of spatial correlation, and reduces the maximum error of timing estimates that originates from sparse spatial grids For attaining the same accuracy, the proposed interpolation reduced CPU time for PCA by 97.7% in a test case.

著者

Kentaro ISHIZU Homare MURAKAMI Stanislav FILIN Hiroshi HARADA

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Communications (ISSN:09168516)

巻号頁・発行日

vol.E93-B, no.12, pp.3311-3322, 2010-12-01

被引用文献数

4

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Selections of radio access networks by terminals are currently not coordinated and utilizations of the radio resources are not balanced. As a result, radio resources on some radio systems are occupied even though others can afford. In this paper, in order to provide a framework to resolve this issue, Cognitive Wireless Router (CWR) system is proposed for distributed management and independent reconfiguration of heterogeneous wireless networks. The proposed system selects appropriate operational frequency bands and radio systems to connect to the Internet in corporation between the CWRs and a server and therefore can provide optimized wireless Internet access easily even in environments without wired networks. The developed prototype system reconfigures the radio devices to connect to the Internet in 27 seconds at most. It is revealed that this reconfiguration time can be shortened to less than 100 ms by elaborating its procedure. It is also clarified that network data speed required at the server to deal with 10,000 CWRs is only 4.1 Mbps.

著者

Yi TANG Junchen JIANG Xiaofei WANG Chengchen HU Bin LIU Zhijia CHEN

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Information and Systems (ISSN:09168532)

巻号頁・発行日

vol.E93-D, no.12, pp.3232-3242, 2010-12-01

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Multi-pattern matching is a key technique for implementing network security applications such as Network Intrusion Detection/Protection Systems (NIDS/NIPSes) where every packet is inspected against tens of thousands of predefined attack signatures written in regular expressions (regexes). To this end, Deterministic Finite Automaton (DFA) is widely used for multi-regex matching, but existing DFA-based researches have claimed high throughput at an expense of extremely high memory cost, so fail to be employed in devices such as high-speed routers and embedded systems where the available memory is quite limited. In this paper, we propose a parallel architecture of DFA called Parallel DFA (PDFA) taking advantage of the large amount of concurrent flows to increase the throughput with nearly no extra memory cost. The basic idea is to selectively store the underlying DFA in memory modules that can be accessed in parallel. To explore its potential parallelism we intensively study DFA-split schemes from both state and transition points in this paper. The performance of our approach in both the average cases and the worst cases is analyzed, optimized and evaluated by numerical results. The evaluation shows that we obtain an average speedup of 100 times compared with traditional DFA-based matching approach.

著者

Yoshiki YUNBE Masayuki MIYAMA Yoshio MATSUDA

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Information and Systems (ISSN:09168532)

巻号頁・発行日

vol.E93-D, no.12, pp.3284-3293, 2010-12-01

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This paper describes an affine motion estimation processor for real-time video segmentation. The processor estimates the dominant motion of a target region with affine parameters. The processor is based on the Pseudo-M-estimator algorithm. Introduction of an image division method and a binary weight method to the original algorithm reduces data traffic and hardware costs. A pixel sampling method is proposed that reduces the clock frequency by 50%. The pixel pipeline architecture and a frame overlap method double throughput. The processor was prototyped on an FPGA; its function and performance were subsequently verified. It was also implemented as an ASIC. The core size is 5.05.0 mm2 in 0.18 µm process, standard cell technology. The ASIC can accommodate a VGA 30 fps video with 120 MHz clock frequency.

著者

Tongsheng GENG Leibo LIU Shouyi YIN Min ZHU Shaojun WEI

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Information and Systems (ISSN:09168532)

巻号頁・発行日

vol.E93-D, no.12, pp.3223-3231, 2010-12-01

被引用文献数

6

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This paper proposes approaches to perform HW/SW (Hardware/Software) partition and parallelization of computing-intensive tasks of the H.264 HiP (High Profile) decoding algorithm on an embedded coarse-grained reconfigurable multimedia system, called REMUS (REconfigurable MUltimedia System). Several techniques, such as MB (Macro-Block) based parallelization, unfixed sub-block operation etc., are utilized to speed up the decoding process, satisfying the requirements of real-time and high quality H.264 applications. Tests show that the execution performance of MC (Motion Compensation), deblocking, and IDCT-IQ (Inverse Discrete Cosine Transform-Inverse Quantization) on REMUS is improved by 60%, 73%, 88.5% in the typical case and 60%, 69%, 88.5% in the worst case, respectively compared with that on XPP PACT (a commercial reconfigurable processor). Compared with ASIC solutions, the performance of MC is improved by 70%, 74% in the typical and in the worst case, respectively, while those of Deblocking remain the same. As for IDCT_IQ, the performance is improved by 17% no matter in the typical or worst case. Relying on the proposed techniques, 1080p@30 fps of H.264 HiP@ Level 4 decoding could be achieved on REMUS when utilizing a 200 MHz working frequency.

著者

Xiaomin JIA Pingjing LU Caixia SUN Minxuan ZHANG

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Information and Systems (ISSN:09168532)

巻号頁・発行日

vol.E93-D, no.12, pp.3211-3222, 2010-12-01

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Chip Multi-Processors (CMPs) emerge as a mainstream architectural design alternative for high performance parallel and distributed computing. Last Level Cache (LLC) management is critical to CMPs because off-chip accesses often require a long latency. Due to its short access latency, well performance isolation and easy scalability, private cache is an attractive design alternative for LLC of CMPs. This paper proposes program Behavior Identification-based Cache Sharing (BICS) for LLC management. BICS is based on a private cache organization for the shorter access latency. Meanwhile, BICS tries to simulate a shared cache organization by allowing evicted blocks of one private LLC to be saved at peer LLCs. This technique is called spilling. BICS identifies cache behavior types of applications at runtime. When a cache block is evicted from a private LLC, cache behavior characteristics of the local application are evaluated so as to determine whether the block is to be spilled. Spilled blocks are allowed to replace some valid blocks of the peer LLCs as long as the interference is within a reasonable level. Experimental results using a full system CMP simulator show that BICS improves the overall throughput by as much as 14.5%, 12.6%, 11.0% and 11.7% (on average 8.8%, 4.8%, 4.0% and 6.8%) over private cache, shared cache, Utility-based Cache Partitioning (UCP) scheme and the baseline spilling-based organization Cooperative Caching (CC) respectively on a 4-core CMP for SPEC CPU2006 benchmarks.

著者

Min ZHU Leibo LIU Shouyi YIN Chongyong YIN Shaojun WEI

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

IEICE TRANSACTIONS on Information and Systems (ISSN:09168532)

巻号頁・発行日

vol.E93-D, no.12, pp.3202-3210, 2010-12-01

被引用文献数

11

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This paper introduces a cycle-accurate Simulator for a dynamically REconfigurable MUlti-media System, called SimREMUS. SimREMUS can either be used at transaction-level, which allows the modeling and simulation of higher-level hardware and embedded software, or at register transfer level, if the dynamic system behavior is desired to be observed at signal level. Trade-offs among a set of criteria that are frequently used to characterize the design of a reconfigurable computing system, such as granularity, programmability, configurability as well as architecture of processing elements and route modules etc., can be quickly evaluated. Moreover, a complete tool chain for SimREMUS, including compiler and debugger, is developed. SimREMUS could simulate 270 k cycles per second for million gates SoC (System-on-a-Chip) and produced one H.264 1080p frame in 15 minutes, which might cost days on VCS (platform: CPU: E5200@ 2.5 Ghz, RAM: 2.0 GB). Simulation showed that 1080p@30 fps of H.264 High Profile@ Level 4 can be achieved when exploiting a 200 MHz working frequency on the VLSI architecture of REMUS.

著者

峰村 今朝明 後藤 理 東山 三樹夫 白井 克彦

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

電子情報通信学会論文誌 A (ISSN:09135707)

巻号頁・発行日

vol.J93-A, no.12, pp.833-834, 2010-12-01

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単母音スペクトルのz変換表示からべき級数展開表現への拡張を検討した.単母音スペクトルはべき級数展開において周波数幅約120 (Hz)ごとに基点を置いた6次関数で表現できる.更にべき級数展開表現を用いた多項式の零点分布により,話者の違いを確認した.

著者

二宮 洋

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

電子情報通信学会論文誌 A (ISSN:09135707)

巻号頁・発行日

vol.J93-A, no.12, pp.828-832, 2010-12-01

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本研究では準ニュートン法に基づくニューラルネットワークの新たな学習法を提案する.従来,準ニュートン法はこう配法に基づく強力な収束特性をもつバッチ学習法であった.近年,大規模なデータを扱う問題への応用としてオンライン準ニュートン法が提案された.本研究ではオンライン準ニュートン法の学習データの与え方を改良することで,準ニュートン法の収束特性を向上させた学習法を提案する.

著者

杉田 泰則 吉川 敏則 相川 直幸

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

電子情報通信学会論文誌 A (ISSN:09135707)

巻号頁・発行日

vol.J93-A, no.12, pp.795-804, 2010-12-01

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ディジタル信号処理の分野において,処理目的に応じてリアルタイムでフィルタ特性を変化させたいことがある.この要求を満たすために,使用時に周波数特性を容易に変えられる可変ディジタルフィルタに関する研究が近年盛んに行われている.本論文では,阻止域において部分的に大きい減衰量を複数もち,かつ,それら大きな減衰の領域がそれぞれ可変な低遅延FIRディジタルフィルタの設計法を提案する.提案法では,重み付き最小二乗法を用い,重み関数を更新して最小二乗問題を繰り返し解くことで準等リプル特性を得る.

著者

服部 一郎 熊谷 佳紀 大橋 剛介

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

電子情報通信学会論文誌 D (ISSN:18804535)

巻号頁・発行日

vol.J93-D, no.12, pp.2678-2682, 2010-12-01

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スケッチ画像検索において入力スケッチの各曲線情報とデータベースのエッジの各曲線情報をフーリエ記述子により記述し,データベース画像内に含まれるオブジェクトの部分検索を可能にする手法を提案する.

著者

杉本 修 内藤 整 酒澤 茂之 羽鳥 好律

出版者

The Institute of Electronics, Information and Communication Engineers

雑誌

電子情報通信学会論文誌 D (ISSN:18804535)

巻号頁・発行日

vol.J93-D, no.12, pp.2620-2632, 2010-12-01

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Full Referenceフレームワークに基づくマルチメディアアプリケーション向けの知覚映像品質評価方式を提案する.本論文では,圧縮符号化による画質劣化に伴うユーザの知覚品質劣化の程度を七つの画像特徴量の重み付き和により定義された客観評価値により推定する.また,フレームレートに応じた客観評価値の補正を行うことにより,テレビ伝送用フォーマットのみを前提とした客観評価方式では対応できていなかった幅広い種類のアーチファクトをもつ低フレームレート画像に対する知覚映像品質の導出を可能としている.計算機シミュレーションにより提案方式の性能評価を行い,MPEG-4 part. 2及びH. 264/AVCエンコーダによりビットレート32 k~512 kbit/sで符号化した3~15 fpsのCIF,QCIF解像度の動画像の主観画質を相関0.88以上で推定可能であることを示す.また,上述のフレームレートに応じた客観評価値の補正により主観画質の推定精度を向上できること,及び7種の特徴量が等しく画質推定に寄与していることを示すことにより,提案方式が幅広い種類の映像に対応可能であることを示す.